diff options
| author | Pengyu Luo <mitltlatltl@gmail.com> | 2025-04-05 18:55:28 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-07-10 16:05:01 +0200 |
| commit | f3a472b914087a8346540c06ddd82bf7feca44ea (patch) | |
| tree | 55e5e86c355b5e1ed562eaafcd264ee931f1695e | |
| parent | 5a867d09f533eaaa3e633012170651c3b23ad40a (diff) | |
arm64: dts: qcom: sm8650: add the missing l2 cache node
[ Upstream commit 4becd72352b6861de0c24074a8502ca85080fd63 ]
Only two little a520s share the same L2, every a720 has their own L2
cache.
Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250405105529.309711-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 72e3dcd495c3..bd91624bd3bf 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -159,13 +159,20 @@ power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&l2_200>; + next-level-cache = <&l2_300>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; #cooling-cells = <2>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu4: cpu@400 { |