diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2025-09-13 23:12:14 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2025-09-13 23:17:18 +0900 |
| commit | f0fbbff7e3082b0e1065aef83cc1418ed2cb1b69 (patch) | |
| tree | 68a7fdba90a2646c19d26c421cd5e9efd0e1d21f | |
| parent | 3760401981f18c427cacea41921620806c06c4bd (diff) | |
gpu: nova-core: require `Send` on `FalconEngine` and `FalconHal`
We want to store the GSP and SEC2 falcon instances inside the `Gpu`
structure, but doing so require these types to implement `Send` for
`pci::Driver` to remain implementable on `NovaCore`, which embeds `Gpu`.
All implementors of `FalconEngine` and `FalconHal` satisfy the
requirements of `Send`, and these traits also already required `Sync`,
so this a minor tweak.
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://lore.kernel.org/r/20250913-nova_firmware-v6-1-9007079548b0@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| -rw-r--r-- | drivers/gpu/nova-core/falcon.rs | 2 | ||||
| -rw-r--r-- | drivers/gpu/nova-core/falcon/hal.rs | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 2dbcdf26697b..b16207e7242f 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -286,7 +286,7 @@ pub(crate) struct PFalcon2Base(()); /// Each engine provides one base for `PFALCON` and `PFALCON2` registers. The `ID` constant is used /// to identify a given Falcon instance with register I/O methods. pub(crate) trait FalconEngine: - Sync + RegisterBase<PFalconBase> + RegisterBase<PFalcon2Base> + Sized + Send + Sync + RegisterBase<PFalconBase> + RegisterBase<PFalcon2Base> + Sized { /// Singleton of the engine, used to identify it with register I/O methods. const ID: Self; diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/falcon/hal.rs index b233bc365882..bba288455617 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -13,7 +13,7 @@ mod ga102; /// Implements chipset-specific low-level operations. The trait is generic against [`FalconEngine`] /// so its `BASE` parameter can be used in order to avoid runtime bound checks when accessing /// registers. -pub(crate) trait FalconHal<E: FalconEngine>: Sync { +pub(crate) trait FalconHal<E: FalconEngine>: Send + Sync { /// Activates the Falcon core if the engine is a risvc/falcon dual engine. fn select_core(&self, _falcon: &Falcon<E>, _bar: &Bar0) -> Result { Ok(()) |