diff options
| author | Ryan Wanner <Ryan.Wanner@microchip.com> | 2025-09-08 13:07:17 -0700 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2025-09-17 19:15:32 +0200 |
| commit | e0237f5635727d64635ec6665e1de9f4cacce35c (patch) | |
| tree | 463a35def2787c6d86052c60a5147b9f65c34118 | |
| parent | af98caeaa7b6ad11eb7b7c8bfaddc769df2889f3 (diff) | |
clk: at91: clk-master: Add check for divide by 3
A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
| -rw-r--r-- | drivers/clk/at91/clk-master.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 7a544e429d34..d5ea2069ec83 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw, { struct clk_master *master = to_clk_master(hw); + if (master->div == MASTER_PRES_MAX) + return DIV_ROUND_CLOSEST_ULL(parent_rate, 3); + return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); } |