diff options
| author | Jianfeng Liu <liujianfeng1994@gmail.com> | 2025-03-11 22:27:50 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-03-12 08:13:15 +0100 |
| commit | d6166ea4cc4943cbabdeeedb13f3545fdba3ebf6 (patch) | |
| tree | 989b6f18aff85d08caf9756b5c705dc1451a053f | |
| parent | 1bfb987d1a54bc139b62261e3698006418835229 (diff) | |
arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7
ArmSoM Sige7 uses the PCI-e AP6275P Wi-Fi 6 module. The pcie@0 node can
be used as Bridge1, so the wifi@0 node is used as a device under the
bridge 1 similar with Khadas Edge 2.
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Link: https://lore.kernel.org/r/20250311142825.2727171-1-liujianfeng1994@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 6a0fffaa26ee..face42bb0d7d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -300,6 +300,22 @@ &pcie2x1l1 { reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x310000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; }; /* phy0 - left ethernet port */ |