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authorMelody Olvera <melody.olvera@oss.qualcomm.com>2025-05-12 13:54:44 -0700
committerBjorn Andersson <andersson@kernel.org>2025-05-13 16:01:05 +0100
commitcd81339e68cb11dbec90fd0d7de12a5c307c1fc7 (patch)
treea4fff177d0ebc0483b719e6e6f118d2641e17a32
parenta18226be95c7ae7c9ec22fd31a6124bef5675c64 (diff)
arm64: dts: qcom: sm8750: Add LLCC node
Add LLCC node for SM8750 SoC. Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-4-d78dca6282a5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sm8750.dtsi18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 149d2ed17641..980ba1ca23c4 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3402,6 +3402,24 @@
#interconnect-cells = <2>;
};
+ system-cache-controller@24800000 {
+ compatible = "qcom,sm8750-llcc";
+ reg = <0x0 0x24800000 0x0 0x200000>,
+ <0x0 0x25800000 0x0 0x200000>,
+ <0x0 0x24c00000 0x0 0x200000>,
+ <0x0 0x25c00000 0x0 0x200000>,
+ <0x0 0x26800000 0x0 0x200000>,
+ <0x0 0x26c00000 0x0 0x200000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
nsp_noc: interconnect@320c0000 {
compatible = "qcom,sm8750-nsp-noc";
reg = <0x0 0x320c0000 0x0 0x13080>;