diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2025-06-25 15:39:37 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-06-26 21:50:23 +0300 |
| commit | ca09800fbbad463c1ff908928367a40e17e65eab (patch) | |
| tree | e373def9f240cd5f8c70b456bacc837bce949ddf | |
| parent | c7cefe479af5d4dcba68ea8f7e25c5a06ebd85b8 (diff) | |
drm/i915/power: relocate {SKL,ICL}_PW_CTL_IDX_TO_PG()
Move the {SKL,ICL}_PW_CTL_IDX_TO_PG() macros from intel_display_regs.h
to intel_display_power_well.c. The mapping from index to PG can be
hidden there.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/18e40b77eeb3517a056f1e567672163ec568ec55.1750855148.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power_well.c | 13 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_regs.h | 12 |
2 files changed, 13 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 5c9ca8141fcc3..9d60dfc4939df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -34,6 +34,19 @@ #include "vlv_iosf_sb_reg.h" #include "vlv_sideband.h" +/* + * PG0 is HW controlled, so doesn't have a corresponding power well control knob + * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 + */ +#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ + ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) +/* + * PG0 is HW controlled, so doesn't have a corresponding power well control knob + * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 + */ +#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ + ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) + struct i915_power_well_regs { i915_reg_t bios; i915_reg_t driver; diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index fdac72fcebeeb..7bd09d981cd2d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -2206,18 +2206,6 @@ enum skl_power_gate { #define SKL_FUSE_STATUS _MMIO(0x42000) #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) -/* - * PG0 is HW controlled, so doesn't have a corresponding power well control knob - * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 - */ -#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ - ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) -/* - * PG0 is HW controlled, so doesn't have a corresponding power well control knob - * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 - */ -#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ - ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) /* Per-pipe DDI Function Control */ |