diff options
| author | Gerhard Uttenthaler <uttenthaler@ems-wuensche.com> | 2023-01-20 12:26:12 +0100 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2023-02-02 17:33:46 +0100 |
| commit | bb89159ce33101abeabd0d67309cf6bdd7691aaa (patch) | |
| tree | 879ab0a2bff030f789bc05160fa7b243f746cd89 | |
| parent | f94a4f97f001d0b665723698c4b4b49174d60b90 (diff) | |
can: ems_pci: Add read/write register and post irq functions
Add functions to read and write SJA1000 registers and also the
post irq routine
Signed-off-by: Gerhard Uttenthaler <uttenthaler@ems-wuensche.com>
Link: https://lore.kernel.org/all/20230120112616.6071-5-uttenthaler@ems-wuensche.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
| -rw-r--r-- | drivers/net/can/sja1000/ems_pci.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/net/can/sja1000/ems_pci.c b/drivers/net/can/sja1000/ems_pci.c index 5748c24dd137..0d6289fda447 100644 --- a/drivers/net/can/sja1000/ems_pci.c +++ b/drivers/net/can/sja1000/ems_pci.c @@ -172,6 +172,24 @@ static void ems_pci_v2_post_irq(const struct sja1000_priv *priv) writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR); } +static u8 ems_pci_v3_read_reg(const struct sja1000_priv *priv, int port) +{ + return readb(priv->reg_base + port); +} + +static void ems_pci_v3_write_reg(const struct sja1000_priv *priv, + int port, u8 val) +{ + writeb(val, priv->reg_base + port); +} + +static void ems_pci_v3_post_irq(const struct sja1000_priv *priv) +{ + struct ems_pci_card *card = (struct ems_pci_card *)priv->priv; + + writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR); +} + /* Check if a CAN controller is present at the specified location * by trying to set 'em into the PeliCAN mode */ @@ -330,10 +348,14 @@ static int ems_pci_add_card(struct pci_dev *pdev, priv->read_reg = ems_pci_v1_read_reg; priv->write_reg = ems_pci_v1_write_reg; priv->post_irq = ems_pci_v1_post_irq; - } else { + } else if (card->version == 2) { priv->read_reg = ems_pci_v2_read_reg; priv->write_reg = ems_pci_v2_write_reg; priv->post_irq = ems_pci_v2_post_irq; + } else { + priv->read_reg = ems_pci_v3_read_reg; + priv->write_reg = ems_pci_v3_write_reg; + priv->post_irq = ems_pci_v3_post_irq; } /* Check if channel is present */ |