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| author | Mark Brown <broonie@kernel.org> | 2024-05-29 11:07:55 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-05-29 11:07:55 +0100 |
| commit | ab0b5a99d371da201e65640a94d68c5322d9d6bd (patch) | |
| tree | 16a6bc45f410f9e1750cb2fd6f3d0efe0200441f | |
| parent | 060bbd65dd4b4bcd519f6c470ec71fc58f9a6190 (diff) | |
| parent | 837e53f766fe9423fcb4e0eacbb3b7ff0e33103c (diff) | |
Add optional reset control for Cadence SPI
Merge series from Ji Sheng Teoh <jisheng.teoh@starfivetech.com>:
The first patch adds optional reset control to support assertion and
deassertion of reset signal to properly bring the SPI device into an
operating condition.
The second patch documents the optional reset control into dt-bindings.
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-cadence.yaml | 7 | ||||
| -rw-r--r-- | drivers/spi/spi-cadence.c | 13 |
2 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index d4b61b0e8301f..8de96abe9da12 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -55,6 +55,13 @@ properties: label: description: Descriptive name of the SPI controller. + resets: + maxItems: 1 + + reset-names: + items: + - const: spi + required: - compatible - reg diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index e5140532071d2..4eacf3f6e031e 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -18,6 +18,7 @@ #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/reset.h> #include <linux/spi/spi.h> /* Name of this driver */ @@ -111,6 +112,7 @@ * @dev_busy: Device busy flag * @is_decoded_cs: Flag for decoder property set or not * @tx_fifo_depth: Depth of the TX FIFO + * @rstc: Optional reset control for SPI controller */ struct cdns_spi { void __iomem *regs; @@ -125,6 +127,7 @@ struct cdns_spi { u8 dev_busy; u32 is_decoded_cs; unsigned int tx_fifo_depth; + struct reset_control *rstc; }; /* Macros for the SPI controller read/write */ @@ -588,6 +591,16 @@ static int cdns_spi_probe(struct platform_device *pdev) goto remove_ctlr; } + xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi"); + if (IS_ERR(xspi->rstc)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(xspi->rstc), + "Cannot get SPI reset.\n"); + goto remove_ctlr; + } + + reset_control_assert(xspi->rstc); + reset_control_deassert(xspi->rstc); + if (!spi_controller_is_target(ctlr)) { xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk"); if (IS_ERR(xspi->ref_clk)) { |