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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-09-12 09:53:27 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-09-12 09:53:27 +0200 |
| commit | 9bb55594efaf9feb299675a9d007f878f13f8b9e (patch) | |
| tree | 090bc90442575517afde8e6d52c3cecd1146f664 | |
| parent | cc55fc58fc1b7f405003fd2ecf79e74653461f0b (diff) | |
| parent | a24cd110e664396061b0a72930734bf419bf88c4 (diff) | |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag4' into renesas-clk-for-v6.18
Renesas RZ/G3E USB3.0 Core Clock DT Binding Definitions
USB3.0 core clock DT binding definitions for the Renesas RZ/G3E
(R9A09G047) SoC, shared by driver and DT source files.
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h index a27132f9a6c8..f165df8a6f5a 100644 --- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -20,5 +20,7 @@ #define R9A09G047_SPI_CLK_SPI 9 #define R9A09G047_GBETH_0_CLK_PTP_REF_I 10 #define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 +#define R9A09G047_USB3_0_REF_ALT_CLK_P 12 +#define R9A09G047_USB3_0_CLKCORE 13 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |