diff options
author | Jimmy Kizito <Jimmy.Kizito@amd.com> | 2022-06-13 10:19:18 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-05 16:16:22 -0400 |
commit | 9a714dcf1039d1142a1c3ad81db09d2706230e00 (patch) | |
tree | cdcc832d179e7733cb37c9eab1501b94fd1c01c3 | |
parent | e9a7d236eaaeb1cdfe20e583e2e1899b26d7469c (diff) |
drm/amd/display: Disable TBT3 DSC work around by default.
[Why]
Some TBT3 docks have DPOAs which report USB4 capability and are expected
to support USB4 DPOA features such as FEC/DSC.
[How]
By default, do not override FEC/DSC capabilities reported by TBT3 docks.
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index e0660e7356c9d..07e5b316fbde5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -5553,7 +5553,7 @@ static bool retrieve_link_cap(struct dc_link *link) * only if required. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && - !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around && + link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around && link->dpcd_caps.is_branch_dev && link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 && diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 30379e5ff898b..337bbd4c66429 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -542,7 +542,7 @@ union dpia_debug_options { uint32_t force_non_lttpr:1; /* bit 1 */ uint32_t extend_aux_rd_interval:1; /* bit 2 */ uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ - uint32_t disable_force_tbt3_work_around:1; /* bit 4 */ + uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ uint32_t reserved:27; } bits; uint32_t raw; |