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| author | Andreas Schwab <schwab@suse.de> | 2025-07-10 15:32:18 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-07-24 08:56:32 +0200 |
| commit | 95a13b0a6b042ac5333b67f59af1dffe7b71137b (patch) | |
| tree | b12cf656871f786b8ee59c1a752fd7822e89bc37 | |
| parent | 32b14e757404ca0a259214725fe82f985b9aed81 (diff) | |
riscv: traps_misaligned: properly sign extend value in misaligned load handler
[ Upstream commit b3510183ab7d63c71a3f5c89043d31686a76a34c ]
Add missing cast to signed long.
Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/riscv/kernel/traps_misaligned.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index d14bfc23e315..4128aa5e0c76 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -436,7 +436,7 @@ int handle_misaligned_load(struct pt_regs *regs) } if (!fp) - SET_RD(insn, regs, val.data_ulong << shift >> shift); + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift); else if (len == 8) set_f64_rd(insn, regs, val.data_u64); else |