diff options
| author | Nick Chan <towinchenmi@gmail.com> | 2025-02-20 20:21:44 +0800 |
|---|---|---|
| committer | Sven Peter <sven@svenpeter.dev> | 2025-04-13 12:46:30 +0200 |
| commit | 93669da1d1e35cb8d4df7e7f9765721c998521e7 (patch) | |
| tree | 262edba01c0eb7277e1fb7a064a5da81f7092c2c | |
| parent | 1ed7edcf5caa4332e33c4f43a1a36750ac61a652 (diff) | |
arm64: dts: apple: t7001: Add CPU caches
Add information about CPU caches in Apple A8X SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-3-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
| -rw-r--r-- | arch/arm64/boot/dts/apple/t7001.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index 8e2c67e19c41..a2efa81305df 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -39,6 +39,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -49,6 +52,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu2: cpu@2 { @@ -59,6 +65,16 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; }; }; |