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authorChris Packham <chris.packham@alliedtelesis.co.nz>2025-06-19 13:07:53 +1200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2025-07-02 13:18:44 +0200
commit787981d189a04c90b66e2d334bbdf83e9f284340 (patch)
tree428b00f52a1ab1fbb516990c609396ce38d46a4f
parent1931e4ccb9dcfd1b45508ba59d20fa25175914a0 (diff)
mips: dts: realtek: Add watchdog
The RTL9300 has an integrated watchdog. Add this to the devicetree. This is taken from openwrt[1] the only difference is removing the unnecessary second cell from the interrupts. [1] - https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/dts/rtl930x.dtsi Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-rw-r--r--arch/mips/boot/dts/realtek/rtl930x.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi
index 74b30704f188..77a854034aba 100644
--- a/arch/mips/boot/dts/realtek/rtl930x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi
@@ -142,6 +142,20 @@
clocks = <&lx_clk>;
};
+ watchdog0: watchdog@3260 {
+ compatible = "realtek,rtl9300-wdt";
+ reg = <0x3260 0xc>;
+
+ realtek,reset-mode = "soc";
+
+ clocks = <&lx_clk>;
+ timeout-sec = <30>;
+
+ interrupt-parent = <&intc>;
+ interrupt-names = "phase1", "phase2";
+ interrupts = <5>, <6>;
+ };
+
snand: spi@1a400 {
compatible = "realtek,rtl9301-snand";
reg = <0x1a400 0x44>;