diff options
| author | Phil Elwell <phil@raspberrypi.com> | 2025-02-23 13:56:14 +0100 |
|---|---|---|
| committer | Florian Fainelli <florian.fainelli@broadcom.com> | 2025-02-25 11:23:49 -0800 |
| commit | 768953614c1c13fdf771be5742f1be573eea8fa4 (patch) | |
| tree | 9516675570423d5714e5b6c154478c185aff7f41 | |
| parent | 2014c95afecee3e76ca4a56956a936e23283f05b (diff) | |
arm64: dts: bcm2712: PL011 UARTs are actually r1p5
The ARM PL011 UART instances in BCM2712 are r1p5 spec, which means they
have 32-entry FIFOs. The correct periphid value for this is 0x00341011.
Thanks to N Buchwitz for pointing this out.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20250223125614.3592-3-wahrenst@gmx.net
Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for Raspberry Pi 5")
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
| -rw-r--r-- | arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 689c82b7f596..9e610a89a337 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -227,7 +227,7 @@ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_uart>, <&clk_vpu>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; |