diff options
| author | Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> | 2024-02-10 17:28:54 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-02-14 00:14:49 -0600 |
| commit | 74851b7f180a0534f25c3d0b744a92b2e3cb6dd2 (patch) | |
| tree | a3db5723974a937809ccdc7d6a14b50af0fc6a3e | |
| parent | 70d6c14f52ff14742d5260b825fd76d047166a75 (diff) | |
ARM: dts: qcom: msm8226: Add CPU and SAW/ACC nodes
Add CPU and SAW/ACC nodes to enable SMP on MSM8226.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
[luca: update some nodes to fix dtbs_check errors, reorder, cleanup]
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240210-msm8226-cpu-v2-3-5d9cb4c35204@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 6896318e6612..8fae6058bf58 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -34,6 +34,57 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + CPU1: cpu@1 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + CPU2: cpu@2 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + }; + + CPU3: cpu@3 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + firmware { scm { compatible = "qcom,scm-msm8226", "qcom,scm"; @@ -185,6 +236,11 @@ reg = <0xf9011000 0x1000>; }; + saw_l2: power-manager@f9012000 { + compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2"; + reg = <0xf9012000 0x1000>; + }; + timer@f9020000 { compatible = "arm,armv7-timer-mem"; reg = <0xf9020000 0x1000>; @@ -243,6 +299,46 @@ }; }; + acc0: power-manager@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + }; + + saw0: power-manager@f9089000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>; + }; + + acc1: power-manager@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + }; + + saw1: power-manager@f9099000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>; + }; + + acc2: power-manager@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + }; + + saw2: power-manager@f90a9000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>; + }; + + acc3: power-manager@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + }; + + saw3: power-manager@f90b9000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>; + }; + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; |