diff options
| author | Kwanghoon Son <k.son@samsung.com> | 2024-08-19 16:55:45 +0900 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-22 08:33:42 +0200 |
| commit | 71e0b08ed2a98e5ab5eb255fc86cda04205b141e (patch) | |
| tree | 8e180702a4724d9ec2419ddf72833fe22f63fc18 | |
| parent | 1e6084cf69b3adefe6591d89bff911eef0c1d6da (diff) | |
arm64: dts: exynosautov9: Add dpum SysMMU
Add System Memory Management Unit(SysMMU) for dpum also called iommu.
This sysmmu is version 7.4, which has same functionality as exynos850.
DPUM has 4 dma channel, each channel is mapped to one iommu.
Signed-off-by: Kwanghoon Son <k.son@samsung.com>
Link: https://lore.kernel.org/r/20240819-add_sysmmu-v1-1-799c0f3f607f@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 599e728248759..b36292a7db640 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -261,6 +261,42 @@ clock-names = "oscclk", "bus"; }; + sysmmu_dpum_0: sysmmu@18c80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18c80000 0x10000>; + interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D0_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + + sysmmu_dpum_1: sysmmu@18c90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18c90000 0x10000>; + interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D1_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + + sysmmu_dpum_2: sysmmu@18ca0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18ca0000 0x10000>; + interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D2_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + + sysmmu_dpum_3: sysmmu@18cb0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18cb0000 0x10000>; + interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D3_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + cmu_core: clock-controller@1b030000 { compatible = "samsung,exynosautov9-cmu-core"; reg = <0x1b030000 0x8000>; |