diff options
| author | Alexey Charkov <alchark@gmail.com> | 2025-05-15 22:38:44 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-06-12 17:25:18 +0200 |
| commit | 6cd594ed969d5cfc7f97029f8ca0d240637ebb8d (patch) | |
| tree | e8c56d83a5a4c5f93f6ce7386f8ccb5868441968 | |
| parent | 1918e51321c0c34341397644512568ac3451e416 (diff) | |
ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
WonderMedia WM8850/WM8950 uses an ARM PL310 cache controller for its
L2 cache, add it.
The parameters have been deduced from vendor's U-boot environment
variables, which the downstream code uses to initialize the
controller. They set the following register values:
aux = 0x3e440000
prefetch_ctrl = 0x70000007
Their initialization code also unconditionally sets the flags
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, so encode those too
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250515-wmt-dts-updates-v2-5-246937484cc8@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/vt8500/wm8850.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi index f741a3e88d74..58109aa05f74 100644 --- a/arch/arm/boot/dts/vt8500/wm8850.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -18,6 +18,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x0>; + next-level-cache = <&l2_cache>; }; }; @@ -308,5 +309,18 @@ reg = <0xd8004000 0x100>; interrupts = <10>; }; + + l2_cache: cache-controller@d9000000 { + compatible = "arm,pl310-cache"; + reg = <0xd9000000 0x1000>; + arm,double-linefill = <1>; + arm,dynamic-clock-gating = <1>; + arm,shared-override; + arm,standby-mode = <1>; + cache-level = <2>; + cache-unified; + prefetch-data = <1>; + prefetch-instr = <1>; + }; }; }; |