diff options
| author | Ajit Pandey <quic_ajipan@quicinc.com> | 2025-04-17 22:37:41 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-05-19 15:33:51 -0500 |
| commit | 654ac800d4ac6bd4bffa7e98997a1e0d336999b1 (patch) | |
| tree | eaab5895b034c9f73ab3cf8d73e1ba726945026d | |
| parent | 299038d824180f21803282e445459ec5d7397c10 (diff) | |
arm64: dts: qcom: sm4450: Add RPMh power domains support
Add device node for RPMh power domains on Qualcomm SM4450 platform.
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250417-sm4450_rpmhpd-v1-3-361846750d3a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm4450.dtsi | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 27453771aa68..d217d922811e 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -10,6 +10,8 @@ #include <dt-bindings/clock/qcom,sm4450-gpucc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -591,6 +593,72 @@ clocks = <&xo_board>; clock-names = "xo"; }; + + rpmhpd: power-controller { + compatible = "qcom,sm4450-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + }; + + rpmhpd_opp_low_svs_l2: opp-96 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; }; cpufreq_hw: cpufreq@17d91000 { |