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authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>2025-03-18 14:35:38 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2025-06-19 15:32:09 +0200
commit5aac41632fffe7eb4708d9e88e203a2cb13283c9 (patch)
tree4a106dd37c30abc3fe35b271ece05ac0e136596b
parente3f71127c6d9b33bd714a957fd62c72abd87c182 (diff)
phy: rockchip: samsung-hdptx: Do no set rk_hdptx_phy->rate in case of errors
[ Upstream commit 1f4d382769e3b38dfc498c806811dae856e40f31 ] Ensure rk_hdptx_ropll_tmds_cmn_config() updates hdptx->rate only after all the other operations have been successful. Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-4-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
-rw-r--r--drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 70526c67ca0f..5547f8df8e71 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -781,9 +781,7 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
{
const struct ropll_config *cfg = NULL;
struct ropll_config rc = {0};
- int i;
-
- hdptx->rate = rate * 100;
+ int ret, i;
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
if (rate == ropll_tmds_cfg[i].bit_rate) {
@@ -842,7 +840,11 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
PLL_PCG_CLK_EN);
- return rk_hdptx_post_enable_pll(hdptx);
+ ret = rk_hdptx_post_enable_pll(hdptx);
+ if (!ret)
+ hdptx->rate = rate * 100;
+
+ return ret;
}
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,