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authorGeert Uytterhoeven <geert+renesas@glider.be>2025-07-08 12:06:13 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-07-08 12:06:13 +0200
commit4590e8dc04e016e7ba796a64445790ff99d29d1d (patch)
tree5550d61256f74a82e8536cafa8d3425c7c5a741b
parented62c3807d3310f555ff02c1cd9b071d69faa38e (diff)
parent5e4e8c1415c181ce311a0b5936ef301edd57c5d1 (diff)
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-dts-for-v6.17
Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared by driver and DT source files.
-rw-r--r--include/dt-bindings/clock/renesas,r9a09g056-cpg.h1
-rw-r--r--include/dt-bindings/clock/renesas,r9a09g057-cpg.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
index f4905b27f8d9..a9af5af9e3a1 100644
--- a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
@@ -20,5 +20,6 @@
#define R9A09G056_USB2_0_CLK_CORE0 9
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
+#define R9A09G056_SPI_CLK_SPI 12
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
index 884dbeb1e139..5346a898ab60 100644
--- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -21,5 +21,6 @@
#define R9A09G057_USB2_0_CLK_CORE1 10
#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11
#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12
+#define R9A09G057_SPI_CLK_SPI 13
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */