diff options
| author | Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> | 2025-03-28 15:58:29 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-05-19 15:33:50 -0500 |
| commit | 435c3642a6a82c774f2897d72e6ed794a1dbaba1 (patch) | |
| tree | 480730870f1d1a9303c12b707ff98a4985dd22f8 | |
| parent | ea172f61f4fdb17aaaf8def980ee309a3b727eea (diff) | |
arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties
Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data
rates used in lane equalization procedure.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250328-preset_v6-v9-1-22cfa0490518@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 2577a0f4dd71..1f0e50b0e6a1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3225,6 +3225,10 @@ phys = <&pcie3_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + operating-points-v2 = <&pcie3_opp_table>; status = "disabled"; @@ -3427,6 +3431,9 @@ phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; }; @@ -3554,6 +3561,8 @@ phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3680,6 +3689,8 @@ phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 { |