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authorJanne Grunau <j@jannau.net>2024-12-03 08:58:01 +0100
committerSven Peter <sven@svenpeter.dev>2025-02-18 17:44:19 +0100
commit3febe9de5ca5267618675650871a626d0901f8cb (patch)
treef42724bb60c667732cfdd85ba388884796956486
parentd08e455a865c99a8050addf4dc001bcfdf1b7b8b (diff)
arm64: dts: apple: Add SPI NOR nvram partition to all devices
All known M1* and M2* devices use an identical SPI NOR flash configuration with a partition containing a non-volatile key:value storage. Use a .dtsi and include it for every device. The nvram partition parameters itself depend on the version of the installed Apple iboot boot loader. m1n1 will fill in the current values provided by Apple's iboot. Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://lore.kernel.org/r/20241203-asahi-spi-dt-v2-5-cd68bfaf0c84@jannau.net Signed-off-by: Sven Peter <sven@svenpeter.dev>
-rw-r--r--arch/arm64/boot/dts/apple/spi1-nvram.dtsi39
-rw-r--r--arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi2
-rw-r--r--arch/arm64/boot/dts/apple/t600x-j375.dtsi2
-rw-r--r--arch/arm64/boot/dts/apple/t8103-jxxx.dtsi2
-rw-r--r--arch/arm64/boot/dts/apple/t8112-jxxx.dtsi2
5 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi
new file mode 100644
index 000000000000..3df2fd3993b5
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Devicetree include for common spi-nor nvram flash.
+//
+// Apple uses a consistent configiguration for the nvram on all known M1* and
+// M2* devices.
+//
+// Copyright The Asahi Linux Contributors
+
+/ {
+ aliases {
+ nvram = &nvram;
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <25000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nvram: partition@700000 {
+ label = "nvram";
+ /* To be filled by the loader */
+ reg = <0x0 0x0>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
index 2e471dfe43cf..22ebc78e120b 100644
--- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
@@ -119,3 +119,5 @@
&fpwm0 {
status = "okay";
};
+
+#include "spi1-nvram.dtsi"
diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi
index 1e5a19e49b08..d5b985ad5679 100644
--- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi
@@ -126,3 +126,5 @@
&pcie0_dart_3 {
status = "okay";
};
+
+#include "spi1-nvram.dtsi"
diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi
index 5988a4eb6efa..8e82231acab5 100644
--- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi
@@ -90,3 +90,5 @@
&nco_clkref {
clock-frequency = <900000000>;
};
+
+#include "spi1-nvram.dtsi"
diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi
index f5edf61113e7..6da35496a4c8 100644
--- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi
+++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi
@@ -79,3 +79,5 @@
&nco_clkref {
clock-frequency = <900000000>;
};
+
+#include "spi1-nvram.dtsi"