diff options
author | Maíra Canal <mcanal@igalia.com> | 2025-03-17 22:01:10 -0300 |
---|---|---|
committer | Maíra Canal <mcanal@igalia.com> | 2025-03-23 11:06:01 -0300 |
commit | 38712c5281ac5f6f27058b825ca62ae69f2e2451 (patch) | |
tree | b484654700018465cdc3d9803b4887713a10c7ea | |
parent | 76dbd0973c555037931d2ed055a4a69e592caad4 (diff) |
dt-bindings: gpu: v3d: Add per-compatible register restrictions
In order to enforce per-SoC register rules, add per-compatible
restrictions. For example, V3D 3.3 (used in brcm,7268-v3d) has a cache
controller (GCA), which is not present in other V3D generations. Declaring
these differences helps ensure the DTB accurately reflect the hardware
design.
The example was using an incorrect order for the register names. This
commit corrects that by enforcing the order established in the register
items description.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250317-v3d-gpu-reset-fixes-v6-2-f3ee7717ed17@igalia.com
-rw-r--r-- | Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 86 |
1 files changed, 73 insertions, 13 deletions
diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml index dc078ceeca9a..6a1a09031983 100644 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml @@ -22,20 +22,12 @@ properties: - brcm,7278-v3d reg: - items: - - description: hub register (required) - - description: core0 register (required) - - description: GCA cache controller register (if GCA controller present) - - description: bridge register (if no external reset controller) minItems: 2 + maxItems: 4 reg-names: - items: - - const: hub - - const: core0 - - enum: [ bridge, gca ] - - enum: [ bridge, gca ] minItems: 2 + maxItems: 4 interrupts: items: @@ -58,6 +50,74 @@ required: - reg-names - interrupts +allOf: + - if: + properties: + compatible: + contains: + const: brcm,2711-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + reg-names: + items: + - const: hub + - const: core0 + - if: + properties: + compatible: + contains: + const: brcm,2712-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + reg-names: + items: + - const: hub + - const: core0 + - if: + properties: + compatible: + contains: + const: brcm,7268-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: GCA cache controller register + - description: bridge register + reg-names: + items: + - const: hub + - const: core0 + - const: gca + - const: bridge + - if: + properties: + compatible: + contains: + const: brcm,7278-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: bridge register + reg-names: + items: + - const: hub + - const: core0 + - const: bridge + additionalProperties: false examples: @@ -66,9 +126,9 @@ examples: compatible = "brcm,7268-v3d"; reg = <0xf1200000 0x4000>, <0xf1208000 0x4000>, - <0xf1204000 0x100>, - <0xf1204100 0x100>; - reg-names = "hub", "core0", "bridge", "gca"; + <0xf1204100 0x100>, + <0xf1204000 0x100>; + reg-names = "hub", "core0", "gca", "bridge"; interrupts = <0 78 4>, <0 77 4>; }; |