diff options
| author | Quentin Schulz <quentin.schulz@cherry.de> | 2025-02-25 12:53:29 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-02-27 14:28:48 +0100 |
| commit | 2db7d29c7b1629ced3cbab3de242511eb3c22066 (patch) | |
| tree | e62f8559e7caec6fd6fb8bd4a518c44f0df6ca08 | |
| parent | 38f4aa34a5f737ea8588dac320d884cc2e762c03 (diff) | |
arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou
UART0 pinmux by default configures GPIO0_B5 in its UART RTS function for
UART0. However, by default on Haikou, it is used as GPIO as UART RTS for
UART5.
Therefore, let's update UART0 pinmux to not configure the pin in that
mode, a later commit will make UART5 request the GPIO pinmux.
Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard")
Cc: stable@vger.kernel.org
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20250225-ringneck-dtbos-v3-1-853a9a6dd597@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts index eb9470a00e54..6d45a19413ce 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -222,6 +222,8 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; |