diff options
| author | Adam Ford <aford173@gmail.com> | 2025-04-15 20:01:32 -0500 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2025-04-25 10:05:04 +0800 |
| commit | 1c98ceb0d75e17aa59308ed0cf46e48b90006241 (patch) | |
| tree | 107214011b78a0d098672022b7d16c4fbc38d9a2 | |
| parent | a747c4dd2a60c4d0179b372032a4b98548135096 (diff) | |
arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ
The Ethernet PHY setup currently assumes that the bootloader will take the
PHY out of reset, but this behavior is not guaranteed across all
bootloaders. Add the reset GPIO to ensure the kernel can properly control
the PHY reset line.
Also configure the PHY IRQ GPIO to enable interrupt-driven link status
reporting, instead of relying on polling.
This ensures more reliable Ethernet initialization and improves PHY event
handling.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 9ba0cb89fa24..ed7a1be4a1a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -78,6 +78,9 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; |