diff options
| author | Nick Chan <towinchenmi@gmail.com> | 2025-02-20 20:21:42 +0800 |
|---|---|---|
| committer | Sven Peter <sven@svenpeter.dev> | 2025-04-13 12:46:30 +0200 |
| commit | 0a52d413afc6236cd120286be8cb44714c36bc3c (patch) | |
| tree | a4e6727b77c6b2664ba8886a43b92bd05dc6f198 | |
| parent | 0af2f6be1b4281385b618cb86ad946eded089ac8 (diff) | |
arm64: dts: apple: s5l8960x: Add CPU caches
Add information about CPU caches in Apple A7 SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-1-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
| -rw-r--r-- | arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index d820b0e43050..5b5175d6978c 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -37,6 +37,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -47,6 +50,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; }; }; |