| Age | Commit message (Collapse) | Author |
|---|
|
|
|
So we enable APIC by default.
|
|
We need to automatically disable linux groups before automatically
enabling apic.
|
|
|
|
We now have a different strategy for EOI depending on trigger mode:
For edge triggered, the behaviour is unchanged; the eoi comes
before the handler so we don't miss interrupts.
For level triggered, the eoi comes after the handler since the high
interrupt line will trigger the interrupt again and stack up, before we mask
it in queue_intr (and we don't risk missing interrupts).
Message-ID: <20250719074547.288203-1-damien@zamaudio.com>
|
|
Avoid reading the ioapic registers for vector and trigger mode,
by introducing an O(1) memory lookup for these properties.
Message-ID: <20250719064116.285288-2-damien@zamaudio.com>
|
|
enabled
In practice this enables APIC by default for x86_64.
|
|
This code may be needed in the future, so add it in now
but keep it disabled. The special EOI handling for
interrupts may only need to be done for one kind of trigger mode.
|
|
Message-ID: <20250712123404.20826-1-damien@zamaudio.com>
|
|
|
|
This avoids race condition with multiple devices raising interrupts
simultaneously on the same IRQ and causing mask to fail.
TESTED: on SMP and UP+apic gnumach, boots to console and receives
a large file over rumpnet on debian hurd-i386.
Message-ID: <20250711065607.208734-1-damien@zamaudio.com>
|
|
We need to wait first for pending to clear before sending
the IPI assert signal. Likewise, if we always do it this
way, we don't need to wait for pending to clear afterward
because next time we will wait again anyway. Deassert does
not seem necessary according to Intel SDM Vol 3, which
says an IPI is sent when ICR low is written.
NB: This is not the same code as for STARTUP or INIT IPIs.
Message-ID: <20250710101341.178343-2-damien@zamaudio.com>
|
|
|
|
include the missing header, fix the warning.
Message-ID: <20250625014727.40695-1-nikic.milos@gmail.com>
|
|
When building without PAE support, phys_addr_t is defined as unsigned long,
but the kdb printf call uses %llx, which expects an unsigned long long.
This triggers a -Wformat warning due to a type mismatch.
Fix this by explicitly casting the phys_addr_t value to unsigned long long,
ensuring the format string and argument type always match.
This avoids build warnings while preserving existing type definitions.
Message-ID: <20250624013544.842-1-nikic.milos@gmail.com>
|
|
The handle_double_fault function is defined in trap.c and called
from x86_64/locore.S, but lacked a prototype, triggering a compiler
warning: 'no previous prototype for handle_double_fault'.
This change adds a forward declaration at the top of trap.c to
satisfy the compiler and clarify the function's external linkage.
No functional changes.
|
|
Compiler warns about it, and its only invoked from this file.
Message-ID: <20250623190708.742-1-nikic.milos@gmail.com>
|
|
0-13 are on rising edge (legacy)
14-N are active-low level triggered.
This allows for PIIX3 chipset to have working IDE,
if we patch hurd/acpi to ignore buggy irq 9 response.
Message-ID: <20250622073329.188167-1-damien@zamaudio.com>
|
|
Reading lapic->error_status.r may have side effects, and we must preserve it. To avoid a compiler warning about err being unused, cast it to (void).
This keeps the behavior intact while eliminating the warning.
Message-ID: <20250619155105.8940-1-nikic.milos@gmail.com>
|
|
Fixing compiler warnings on ktss c-file. Some that only appear when building on 32 bit arch, some that happen regardless of architecture. Changes tested on the 32 bit build.
Message-ID: <20250620212343.9385-1-nikic.milos@gmail.com>
|
|
glibc and hurd servers cope fine, and this allows to have more userland
memory for very large builds.
|
|
The full range between @ and ~ is defined to be potential ANSI
sequences, so ignore them all.
|
|
"modern" software seem to like spitting sequences without checking for
their support in terminfo, leading to various spurious output, see e.g.
https://github.com/takluyver/bash_kernel/issues/107
Just drop anything we don't support, to avoid getting hit.
|
|
It was meant to be the size of the whole ifps, but then it was mistaken as
the xsave size. Switch to that meaning, and add to it the offset as
appropriate.
|
|
i386_XFLOAT_STATE does expect fxsr tag.
|
|
Userland will fall back to 387 support, which is what it should.
|
|
|
|
Message-ID: <20250407201126.1553736-1-etienne.brateau@gmail.com>
|
|
Integrate HPET so host_get_time, host_get_time64, and host_get_uptime64
are more precise. The highest precision can be 10ns when this patch is
applied.
* i386/i386/apic.c: Implement the two high-precision clock interface functions
added in this patch for i386.
* i386/i386at/model_dep.c: Initialize HPET if APIC is defined
* kern/mach_clock.c: Integrate the high-precision clocks to have the
10ns precise time values.
* kern/mach_clock.h: Add two new interface functions for accessing the
high-precision clocks.
Message-ID: <20250324042551.4752-2-zhmingluo@163.com>
|
|
This notably fixes at least a SAVE_HINT call.
|
|
We need the slock initializer in that case.
|
|
Message-ID: <20250111083330.26863-1-gfleury@disroot.org>
|
|
Because we support up to 64 irqs with 2 IOAPICs.
Message-ID: <20241228042008.704671-1-damien@zamaudio.com>
|
|
|
|
Add workaround for broken systems that advertise 8 bit APIC ids
but only match IPIs on 4 bits of the APIC id.
Message-ID: <20241222014306.430098-4-damien@zamaudio.com>
|
|
Fixes ESR==0x8 error on AMD fam15h. Fixed timings.
Cannot locate documentation on correct mode for STARTUP IPI,
but this patch works on AMD hw and qemu.
Message-ID: <20241222014306.430098-3-damien@zamaudio.com>
|
|
Now that things are in place, we switch to parallel init.
The key to this change is that the INIT/STARTUP sequence
is done in one step, and all cpus wake up at the same time.
Synchronisation is done via waiting for individual flags stored
in separate memory locations.
Message-ID: <20241222014306.430098-2-damien@zamaudio.com>
|
|
|
|
|
|
This allocates a constant space for percpu gdts
and copies the first entry to the nth entry on each cpu,
then patches its own copy of the gdt so it can function
independently.
Message-ID: <20241221235456.423860-2-damien@zamaudio.com>
|
|
Previously, we were ignoring cpus that were not enabled
but online-capable.
Message-ID: <20241221023937.384420-1-damien@zamaudio.com>
|
|
This is basically a no-op but ensures we are doing smp
bringup correctly.
Message-ID: <20241210072926.911061-5-damien@zamaudio.com>
|
|
The number is actually a mask bit per cpu.
Message-ID: <20241210072926.911061-2-damien@zamaudio.com>
|
|
Fixes Wincompatible-pointer-types errors on GCC 15.
Signed-off-by: Sergey Bugaev <bugaevc@gmail.com>
Message-ID: <20241210115705.710555-1-bugaevc@gmail.com>
|
|
The condition was intended for non-BSP processors to
disable timer, but apic_id != 0 means it could affect BSP
if its apic id is non-zero. Fixes this bug.
Message-ID: <20241209121706.879984-7-damien@zamaudio.com>
|
|
Since modern x86 cpus only support 4 bits of destination field
in ICR, we could only address up to 16 processors, assuming
their physical APIC ID was < 0x10. Some processors eg AMD fam15h
have physical apic ids starting at 0x10 but only support 4 bits.
So these lapics are unaddressable using physical destination mode.
Therefore, we switch to using logical destinations for IPIs which
gives us 8 bits of unique mask for addressing up to 8 groups of processors.
INIT and STARTUP is not changed here.
Message-ID: <20241209121706.879984-6-damien@zamaudio.com>
|
|
Prepare for smp parallel init where we want to call these
two functions on different cpus at different times.
Message-ID: <20241209121706.879984-5-damien@zamaudio.com>
|
|
Since we just set up the gs segment, we can use
CPU_NUMBER instead of CPU_NUMBER_NO_STACK.
Message-ID: <20241209121706.879984-3-damien@zamaudio.com>
|
|
|
|
The current segmentation already adds -KERNELBASE.
But only when accessing the memory.
Message-ID: <20241209121706.879984-2-damien@zamaudio.com>
|
