diff options
| author | Damien Zammit <damien@zamaudio.com> | 2025-07-10 10:14:13 +0000 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2025-07-10 17:12:14 +0200 |
| commit | b7fbb06f24351501a3f0a1c3a0e27bcbc746b46f (patch) | |
| tree | 1fdb867e572e7ad378227befa00e7ce3c8ea4c47 | |
| parent | 6fbf311687b8eb46f696f380f417157e4486d71d (diff) | |
i386/smp.c: Change order of waiting for pending ICR
We need to wait first for pending to clear before sending
the IPI assert signal. Likewise, if we always do it this
way, we don't need to wait for pending to clear afterward
because next time we will wait again anyway. Deassert does
not seem necessary according to Intel SDM Vol 3, which
says an IPI is sent when ICR low is written.
NB: This is not the same code as for STARTUP or INIT IPIs.
Message-ID: <20250710101341.178343-2-damien@zamaudio.com>
| -rw-r--r-- | i386/i386/smp.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/i386/i386/smp.c b/i386/i386/smp.c index 4513b7f2..dc3a8ba5 100644 --- a/i386/i386/smp.c +++ b/i386/i386/smp.c @@ -54,17 +54,11 @@ static void smp_send_ipi(unsigned logical_id, unsigned vector) cpu_intr_save(&flags); - apic_send_ipi(NO_SHORTHAND, FIXED, LOGICAL, ASSERT, EDGE, vector, logical_id); - do { cpu_pause(); } while(lapic->icr_low.delivery_status == SEND_PENDING); - apic_send_ipi(NO_SHORTHAND, FIXED, LOGICAL, DE_ASSERT, EDGE, vector, logical_id); - - do { - cpu_pause(); - } while(lapic->icr_low.delivery_status == SEND_PENDING); + apic_send_ipi(NO_SHORTHAND, FIXED, LOGICAL, ASSERT, EDGE, vector, logical_id); cpu_intr_restore(flags); } |