diff options
| author | Damien Zammit <damien@zamaudio.com> | 2025-06-22 07:33:46 +0000 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2025-06-22 21:40:53 +0200 |
| commit | 87b6b23c0f55dc0236bd086eca83238e03174624 (patch) | |
| tree | d8fd33b42683c16fca5077989267dbaa791649f7 | |
| parent | 608d1e197188288b54ea443b4a00e966ca0c6c19 (diff) | |
ioapic.c: Fix default polarity and trigger mode for irqs
0-13 are on rising edge (legacy)
14-N are active-low level triggered.
This allows for PIIX3 chipset to have working IDE,
if we patch hurd/acpi to ignore buggy irq 9 response.
Message-ID: <20250622073329.188167-1-damien@zamaudio.com>
| -rw-r--r-- | i386/i386at/ioapic.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c index 5dd2de2e..d0724f76 100644 --- a/i386/i386at/ioapic.c +++ b/i386/i386at/ioapic.c @@ -393,10 +393,11 @@ ioapic_configure(void) */ entry.both.dest = lapic->apic_id.r >> 24; - for (pin = 0; pin < 16; pin++) { + /* ISA legacy IRQs */ + for (pin = 0; pin < 14; pin++) { gsi = pin; - /* ISA legacy IRQs */ + /* Legacy interrupts are on rising edge */ entry.both.trigger = IOAPIC_EDGE_TRIGGERED; entry.both.polarity = IOAPIC_ACTIVE_HIGH; @@ -426,10 +427,11 @@ ioapic_configure(void) } } - for (pin = 16; pin < ngsis; pin++) { + /* 14,15 and PCI IRQs PIRQ A-H */ + for (pin = 14; pin < ngsis; pin++) { gsi = pin; - /* PCI IRQs PIRQ A-H */ + /* ACPI interrupts default to level-triggered active-low */ entry.both.trigger = IOAPIC_LEVEL_TRIGGERED; entry.both.polarity = IOAPIC_ACTIVE_LOW; |