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| author | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2018-12-27 19:01:57 +0000 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2018-12-27 19:01:57 +0000 |
| commit | cab56836b146bc129f1ad43f0393d95a9deca63a (patch) | |
| tree | 4f4e655319bbac78fca170da05275c127429b460 /sysdeps/i386/fpu/feenablxcpt.c | |
| parent | 04ac1241a4cd004872282c2c82ec37fa33925292 (diff) | |
| parent | 82dd75a7f436a19047325d62182590c9f9e23a78 (diff) | |
Merge branch 't/tls' into refs/top-bases/t/tls-threadvar
Diffstat (limited to 'sysdeps/i386/fpu/feenablxcpt.c')
| -rw-r--r-- | sysdeps/i386/fpu/feenablxcpt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sysdeps/i386/fpu/feenablxcpt.c b/sysdeps/i386/fpu/feenablxcpt.c index 0d0377d21a..a4d9862666 100644 --- a/sysdeps/i386/fpu/feenablxcpt.c +++ b/sysdeps/i386/fpu/feenablxcpt.c @@ -1,5 +1,5 @@ /* Enable floating-point exceptions. - Copyright (C) 1999-2016 Free Software Foundation, Inc. + Copyright (C) 1999-2018 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Andreas Jaeger <aj@suse.de>, 1999. @@ -38,7 +38,7 @@ feenableexcept (int excepts) __asm__ ("fldcw %0" : : "m" (*&new_exc)); /* If the CPU supports SSE we set the MXCSR as well. */ - if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0) + if (HAS_CPU_FEATURE (SSE)) { unsigned int xnew_exc; |