diff options
| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-11-07 12:25:32 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2015-01-12 06:30:19 -0500 |
| commit | 8d2c0a593bdefd220be0822fb70de6b8d3bfd39d (patch) | |
| tree | f99ff4ee80aebb75309fad56b244535115d97288 /NEWS | |
| parent | ec4fbd48009314515eb31daaff7c25393f29d62b (diff) | |
powerpc: Add the lock elision using HTM
This patch adds support for lock elision using ISA 2.07 hardware
transactional memory instructions for pthread_mutex primitives.
Similar to s390 version, the for elision logic defined in
'force-elision.h' is only enabled if ENABLE_LOCK_ELISION is defined.
Also, the lock elision code should be able to be built even with
a compiler that does not provide HTM support with builtins.
However I have noted the performance is sub-optimal due scheduling
pressures.
Diffstat (limited to 'NEWS')
| -rw-r--r-- | NEWS | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -19,6 +19,13 @@ Version 2.21 17745, 17746, 17747, 17748, 17775, 17777, 17780, 17781, 17782, 17791, 17793, 17796, 17797, 17806 +* Added support for TSX lock elision of pthread mutexes on powerpc32, powerpc64 + and powerpc64le. This may improve lock scaling of existing programs on + HTM capable systems. The lock elision code is only enabled with + --enable-lock-elision=yes. Also, the TSX lock elision implementation for + powerpc will issue a transaction abort on every syscall to avoid side + effects being visible outside transactions. + * Optimized strcpy, stpcpy, strchrnul and strrchr implementations for AArch64. Contributed by ARM Ltd. |