blob: 38f397bebe52d955b2fa4062a4833a4042c962e2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
|
/*
* XIOHV5.12 power sequence
* Copyright (C) 2012 Avencall
* Authors:
* Jean Marc Ouvrard
* Noe Rubinstein
* Guillaume Knispel
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HARDWARE_H
#define HARDWARE_H
#include <io430x22x4.h>
// In signal names, - are replaced by _
// used in PORT1
#define START_SW1_N BIT0
#define V1P2_CORE_EN_N BIT1
#define RST_SW2_N BIT2
#define WDT_TOUT_N BIT3
// used in PORT2
#define CK410_PWR_GD_N BIT0
#define GP24 BIT1
#define CPU_VCCP_EN_N BIT2
#define GREEN_LED_N BIT3
#define RED_LED_N BIT4
#define SYS_RESET_N BIT5
#define IMCH_PWRBTN_N BIT6
#define IMCH_RSMRST_N BIT7
// used in PORT3
#define VCC3 BIT0
#define I2_CSMBDAT BIT1
#define I2C_SMBCLK BIT2
#define SYS_PWR_OK BIT3
#define MSP_BSL_TXD BIT4
#define MSP_BSL_RXD BIT5
#define P1V8_PGOOD BIT6
#define VRMPWRGD BIT7
// used in PORT4
#define SLP_S3_N BIT0
#define ATX_PWROK BIT1
#define CMDPWR BIT2
#define V1P0 BIT3
#define V1P2 BIT4
#define V1P8_DDR BIT5
#define V2P5 BIT6
#define V1P8_CMD BIT7
/* Information Config see datasheet
PxOUT_INIT //Init Output data of portx
PxDIR_INIT //Init of Portx Data-Direction Reg (Out=1 / Inp=0)
PxSEL_INIT //Px-Modules:
PxREN_INIT //Pull up resistor
PxIE_INIT //Interrupt Enable (0=dis 1=enabled)
PxIES_INIT //Interrupt Edge Select (0=pos 1=neg)
*/
// NOTES:
//
// * V1P2_CORE_EN_N is initialized as an output high for a reason!
//
// ATX specifies that there can be as much as 20 ms between 5V reaching
// its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by
// 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate.
// ISL6545 can ramp up its output between ~ 10 and 17 ms after
// Power On Reset (defined by an high enough voltage on the 5V plane),
// and might do it even before.
// So when only using the pull-up to 3.3V rail and with an ATX
// power supply that has a particular timing, V1P2 would start to
// ramp up too early.
// PORT1
#define P1OUT_INIT (START_SW1_N | RST_SW2_N | V1P2_CORE_EN_N)
#define P1DIR_INIT (V1P2_CORE_EN_N)
#define P1SEL_INIT 0
#define P1REN_INIT (START_SW1_N | RST_SW2_N)
#define P1IE_INIT 0
#define P1IES_INIT 0
// PORT2
#define P2OUT_INIT (CK410_PWR_GD_N | CPU_VCCP_EN_N | GREEN_LED_N \
| RED_LED_N | IMCH_RSMRST_N)
#define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N)
#define P2REN_INIT (CK410_PWR_GD_N | IMCH_RSMRST_N)
#define P2SEL_INIT 0
#define P2IE_INIT 0
#define P2IES_INIT 0
// PORT3
#define P3OUT_INIT 0
#define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD)
#define P3SEL_INIT 0
// PORT4
#define P4OUT_INIT (SLP_S3_N)
#define P4DIR_INIT (CMDPWR | V1P8_CMD)
#define P4REN_INIT (SLP_S3_N)
#define P4SEL_INIT 0
#endif //HARDWARE_H
|
