diff options
author | Guillaume Knispel <gknispel@avencall.com> | 2012-07-26 21:30:04 +0200 |
---|---|---|
committer | Guillaume Knispel <gknispel@avencall.com> | 2012-07-26 21:30:04 +0200 |
commit | 9dc6c28545daf15e8f7e67e5fa9b5cf6730a0585 (patch) | |
tree | 6dd0ca8189df15c7486d438f3c8313979953b5cc | |
parent | 92a55b1a757353d598f2d79665f48a596a7593c2 (diff) |
make power sequence work quite well
Properly reset the EP80579 by driving SYS_RESET_N inside the
reset state machine and IMCH_RSMRST_N correctly back in the main
state machine.
-rw-r--r-- | hardware.h | 7 | ||||
-rw-r--r-- | main.c | 16 |
2 files changed, 10 insertions, 13 deletions
@@ -97,9 +97,10 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) // PORT2 #define P2OUT_INIT (CK410_PWR_GD_N | CPU_VCCP_EN_N | GREEN_LED_N \ - | RED_LED_N | IMCH_RSMRST_N | SYS_RESET_N) -#define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N) -#define P2REN_INIT (CK410_PWR_GD_N | IMCH_RSMRST_N | SYS_RESET_N) + | RED_LED_N | SYS_RESET_N) +#define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N \ + | IMCH_RSMRST_N) +#define P2REN_INIT (CK410_PWR_GD_N | SYS_RESET_N) #define P2SEL_INIT 0 #define P2IE_INIT 0 #define P2IES_INIT 0 @@ -97,16 +97,16 @@ int main(void) break; case RST_STATE: - SetBit(P2DIR, IMCH_RSMRST_N); - ClrBit(P2OUT, IMCH_RSMRST_N); - Timer2 = 100; + ClrBit(P2REN, SYS_RESET_N); + SetBit(P2DIR, SYS_RESET_N); + ClrBit(P2OUT, SYS_RESET_N); + Timer2 = 150; resetState = RST_WAIT; break; case RST_WAIT: if (Timer2 == 0) { - ClrBit(P2DIR, IMCH_RSMRST_N); - SetBit(P2OUT, IMCH_RSMRST_N); + SetBit(P2OUT, SYS_RESET_N); if (SW2State == 0) resetState = ON_STATE; } @@ -130,9 +130,6 @@ int main(void) if (SW1State || TENSION_EXPIRED) state = STOP; if ((P4IN & ATX_PWROK) && TENSION_WAIT(bV2P5 && bVCC3)) { - SetBit(P2DIR, SYS_RESET_N); //modif jmo 25072012 - ClrBit(P2OUT, SYS_RESET_N); //modif jmo 25072012 - ClrBit(P1OUT, V1P2_CORE_EN_N); Timer1 = 30; state = WAIT_V1P2; @@ -153,8 +150,7 @@ int main(void) if (SW1State) state = STOP; if (Timer1 < 20) { - SetBit(P2DIR, IMCH_RSMRST_N); - ClrBit(P2OUT, IMCH_RSMRST_N); + SetBit(P2OUT, IMCH_RSMRST_N); state = WAIT_V1P8; } break; |