1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
|
/*
* Copyright (c) 2012-2014 Richard Braun.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*
* Atomic operations.
*/
#ifndef _X86_ATOMIC_H
#define _X86_ATOMIC_H
#define ATOMIC_ADD(ptr, delta) \
asm volatile("lock add %1, %0" \
: "+m" (*(ptr)) \
: "r" (delta))
#define ATOMIC_FETCHADD(ptr, oldval, delta) \
asm volatile("lock xadd %1, %0" \
: "+m" (*(ptr)), "=r" (oldval) \
: "1" (delta) \
: "memory")
#define ATOMIC_AND(ptr, bits) \
asm volatile("lock and %1, %0" \
: "+m" (*(ptr)) \
: "r" (bits))
#define ATOMIC_OR(ptr, bits) \
asm volatile("lock or %1, %0" \
: "+m" (*(ptr)) \
: "r" (bits))
/* The xchg instruction doesn't need a lock prefix */
#define ATOMIC_SWAP(ptr, oldval, newval) \
asm volatile("xchg %1, %0" \
: "+m" (*(ptr)), "=r" (oldval) \
: "1" (newval) \
: "memory")
#define ATOMIC_CAS(ptr, oldval, predicate, newval) \
asm volatile("lock cmpxchg %3, %0" \
: "+m" (*(ptr)), "=a" (oldval) \
: "1" (predicate), "r" (newval) \
: "memory")
static inline void
atomic_add_uint(volatile unsigned int *ptr, int delta)
{
ATOMIC_ADD(ptr, delta);
}
/*
* Implies a full memory barrier.
*/
static inline unsigned int
atomic_fetchadd_uint(volatile unsigned int *ptr, int delta)
{
unsigned int oldval;
ATOMIC_FETCHADD(ptr, oldval, delta);
return oldval;
}
static inline void
atomic_and_uint(volatile unsigned int *ptr, unsigned int bits)
{
ATOMIC_AND(ptr, bits);
}
static inline void
atomic_or_uint(volatile unsigned int *ptr, unsigned int bits)
{
ATOMIC_OR(ptr, bits);
}
/*
* Implies a full memory barrier.
*/
static inline unsigned int
atomic_swap_uint(volatile unsigned int *ptr, unsigned int newval)
{
unsigned int oldval;
ATOMIC_SWAP(ptr, oldval, newval);
return oldval;
}
/*
* Implies a full memory barrier.
*/
static inline unsigned int
atomic_cas_uint(volatile unsigned int *ptr, unsigned int predicate,
unsigned int newval)
{
unsigned int oldval;
ATOMIC_CAS(ptr, oldval, predicate, newval);
return oldval;
}
static inline void
atomic_add_ulong(volatile unsigned long *ptr, long delta)
{
ATOMIC_ADD(ptr, delta);
}
/*
* Implies a full memory barrier.
*/
static inline unsigned long
atomic_fetchadd_ulong(volatile unsigned long *ptr, long delta)
{
unsigned long oldval;
ATOMIC_FETCHADD(ptr, oldval, delta);
return oldval;
}
static inline void
atomic_and_ulong(volatile unsigned long *ptr, unsigned long bits)
{
ATOMIC_AND(ptr, bits);
}
static inline void
atomic_or_ulong(volatile unsigned long *ptr, unsigned long bits)
{
ATOMIC_OR(ptr, bits);
}
/*
* Implies a full memory barrier.
*/
static inline unsigned long
atomic_swap_ulong(volatile unsigned long *ptr, unsigned long newval)
{
unsigned long oldval;
ATOMIC_SWAP(ptr, oldval, newval);
return oldval;
}
/*
* Implies a full memory barrier.
*/
static inline unsigned long
atomic_cas_ulong(volatile unsigned long *ptr, unsigned long predicate,
unsigned long newval)
{
unsigned long oldval;
ATOMIC_CAS(ptr, oldval, predicate, newval);
return oldval;
}
#endif /* _X86_ATOMIC_H */
|