diff options
| author | Richard Braun <rbraun@sceen.net> | 2017-05-23 20:32:30 +0200 |
|---|---|---|
| committer | Richard Braun <rbraun@sceen.net> | 2017-05-23 20:37:53 +0200 |
| commit | d3742166baf0eca95875c61d5a72174b8e7bd0b2 (patch) | |
| tree | 38ec7524b58c3e65af5e8bb40e978fca254a9d78 /arch/x86/machine/pic.c | |
| parent | b5451753e15bbe0a986ed32297f4a5de5c7e77ea (diff) | |
x86/trap: rework to allow registering trap handlers
Diffstat (limited to 'arch/x86/machine/pic.c')
| -rw-r--r-- | arch/x86/machine/pic.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/machine/pic.c b/arch/x86/machine/pic.c index db26a166..412135cc 100644 --- a/arch/x86/machine/pic.c +++ b/arch/x86/machine/pic.c @@ -57,8 +57,8 @@ pic_setup(void) io_write_byte(PIC_SLAVE_CMD, PIC_ICW1_INIT | PIC_ICW1_IC4); /* ICW 2 */ - io_write_byte(PIC_MASTER_IMR, TRAP_PIC_BASE); - io_write_byte(PIC_SLAVE_IMR, TRAP_PIC_BASE + PIC_NR_INTRS); + io_write_byte(PIC_MASTER_IMR, TRAP_INTR_FIRST); + io_write_byte(PIC_SLAVE_IMR, TRAP_INTR_FIRST + PIC_NR_INTRS); /* ICW 3 - Set up cascading */ io_write_byte(PIC_MASTER_IMR, 1 << PIC_SLAVE_INTR); @@ -96,7 +96,7 @@ pic_spurious_intr(struct trap_frame *frame) unsigned long intr; uint8_t isr; - intr = frame->vector - TRAP_PIC_BASE; + intr = frame->vector - TRAP_INTR_FIRST; assert((intr == PIC_SPURIOUS_INTR) || (intr == (PIC_NR_INTRS + PIC_SPURIOUS_INTR))); |