x86: remove store memory barriers

Use a compiler barrier instead of a memory barrier to enforce program order.
The x86 architecture normally enforces ordering on stores. There are
exceptions but they're currently not supported.

1 files changed, 2 insertions, 1 deletions

diff --git a/arch/x86/machine/cpu.c b/arch/x86/machine/cpu.c
index 0d1a9f38..eb0eb7e1 100644
--- a/arch/x86/machine/cpu.c
+++ b/arch/x86/machine/cpu.c
@@ -527,7 +527,8 @@ cpu_mp_start_aps(void)
 
         boot_ap_id = i;
         boot_ap_stack_addr = cpu->boot_stack;
-        mb_store();
+
+        barrier();
 
         lapic_ipi_init_assert(cpu->apic_id);
         cpu_delay(200);