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2018-12-14Merge branch 'clk-qcom-sdm845-lpass' into clk-nextStephen Boyd
- Qualcomm SDM845 audio subsystem clks * clk-qcom-sdm845-lpass: clk: qcom: Add lpass clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM LPASS clock bindings dt-bindings: clock: Update GCC bindings for protected-clocks
2018-12-14Merge branches 'clk-qcom-kconfig', 'clk-qcom-gpucc', 'clk-qcom-qcs404-rpm', ↵Stephen Boyd
'clk-qcom-spi' and 'clk-qcom-videocc-binding' into clk-next - Qualcomm SDM845 GPU clock controllers - Qualcomm QCS404 RPM clk support * clk-qcom-kconfig: clk: qcom: Move to menuconfig and reduce lines * clk-qcom-gpucc: dt-bindings: clock: qcom: Fix the xo parent in gpucc example clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6 clk: qcom: Add a dummy enable function for GX gdsc clk: qcom: gdsc: Don't override existing gdsc pd functions clk: qcom: Add graphics clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Graphics clock bindings * clk-qcom-qcs404-rpm: clk: qcom: smd: Add support for QCS404 rpm clocks * clk-qcom-spi: clk: qcom: msm8916: Additional clock rates for spi * clk-qcom-videocc-binding: dt-bindings: clock: Require #reset-cells in sdm845-videocc
2018-12-14ASoC: qdsp6: dt-bindings: Add q6afe display_port dt bindingRohit kumar
This patch adds bindings required for DISPLAY_PORT_RX port on AFE. Signed-off-by: Rohit kumar <rohitkr@codeaurora.org> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-12-14dt-bindings: pinctrl: k3: Introduce pinmux definitionsVignesh R
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for defining pinmux configs in human readable form, instead of raw-coded hex values. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-13dt-bindings: clock: add imx8qxp lpcg clock bindingAisheng Dong
The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. Note: This level of clock gating is provided after the clocks are generated by the SCU resources and clock controls. Thus even if the clock is enabled by these control bits, it might still not be running based on the base resource. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13dt-bindings: clock: imx8qxp: add SCU clock IDsAisheng Dong
Add IMX8QXP SCU clock IDs. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-12Merge tag 'imx-drivers-4.21' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers i.MX drivers change for 4.21: - A series from Aisheng that improves SCU power domain bindings by defining '#power-domain-cells' as 1, and adds i.MX8 SCU power domain driver support on top of it. - A series from Lucas that updates gpcv2 driver for scalability and adds i.MX8MQ support into the driver. - Increase gpc driver GPC_CLK_MAX definition to 7, as DISPLAY power domain on imx6sx has 7 clocks. * tag 'imx-drivers-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: gpc: Increase GPC_CLK_MAX to 7 soc: imx: gpcv2: add support for i.MX8MQ SoC soc: imx: gpcv2: move register access table to domain data soc: imx: gpcv2: prefix i.MX7 specific defines firmware: imx: add SCU power domain driver firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'renesas-drivers-for-v4.21' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Renesas ARM Based SoC Drivers Updates for v4.21 SYSC Driver: * Common - Fix power domain control after system resume - Merge PM Domain registration and linking - Remove rcar_sysc_power_{down,up}() helpers * R-Car E3 (r8a77990) SoC - Fix initialization order of 3DG-{A,B} * R-Car V3H (r8a77980) SoC - Correct A3VIP[012] power domain hierarchy - Correct names of A2DP[01] power domains * R-Car V3M (r8a77970) SoC - Correct names of A2DP/A2CN power domains - emove non-existent CR7 power domain * R-Car M3-N (r8a77965) SoC - Remove non-existent A3IR power domain * tag 'renesas-drivers-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: rcar-sysc: Fix power domain control after system resume soc: renesas: rcar-sysc: Merge PM Domain registration and linking soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B} soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain soc: renesas: r8a77965-sysc: Remove non-existent A3IR power domain Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'amlogic-dt-2' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt ARM: dts: Amlogic updates for v4.21, round 2 Highlights - add CPU OPP tables - timers: add global timer and TWD * tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson: meson8b: add the CPU OPP tables ARM: dts: meson: meson8: add the CPU OPP table ARM: dts: meson8b: add the Cortex-A5 global timer ARM: dts: meson8b: add the ARM TWD timer ARM: dts: meson8: add the Cortex-A9 global timer ARM: dts: meson8: add the ARM TWD timer ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals dt-bindings: clock: meson8b: export the CPU post dividers Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'imx7ulp-dt-4.21' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt i.MX7ULP device tree for 4.21: - It includes the initial device tree for i.MX7ULP SoC and EVK board support. * tag 'imx7ulp-dt-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx: add imx7ulp evk support ARM: dts: imx: add common imx7ulp dtsi support dt-bindings: fsl: add imx7ulp pm related components bindings dt-bindings: fsl: add compatible for imx7ulp evk clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12regulator: act8945a-regulator: Implement PM functionalitiesBoris Brezillon
The regulator supports a dedicated suspend mode. Implement the appropriate ->set_suspend_xx() hooks, add support for ->set_mode(), and provide basic PM ops functionalities to setup the regulator in a suspend state when the system is entering suspend. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [claudiu.beznea@microchip.com: remove shutdown function, use dev_pm_ops, fix checkpatch warning, adapt commit message, add LDO modes support, move modes constants to active-semi,8945a-regulator.h, remove rdevs from struct act8945a_pmic, add op_mode to act8945a_pmic] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-12-11clk: qcom: Add missing msm8998 resetsJeffrey Hugo
commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") missed two USB2 resets. Add them. Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11Merge tag 'tegra-for-4.21-dt-bindings' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt dt-bindings: Changes for v4.21-rc1 This contains a few cleanups of and additions to existing device tree bindings, such as XUSB, EMC, PMC and thermal. * tag 'tegra-for-4.21-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: tegra186-pmc: Add interrupt controller properties dt-bindings: thermal: tegra-bpmp: Add Tegra194 support dt: bindings: Move tegra20-emc binding to memory-controllers directory dt: bindings: tegra20-emc: Document clock property dt: bindings: tegra20-emc: Document interrupt property dt-bindings: usb: xhci-tegra: Add power-domain details Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-10clk: imx6q: add DCICx clocks gateAnson Huang
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks gate in CCM_CCGR0 register, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-07dt-bindings: tegra186-gpio: Add Tegra186 specific prefixThierry Reding
Subsequent generations of Tegra, such as Tegra194, contain a completely different set of GPIOs. In order to clarify that the Tegra186 defines are indeed specific to Tegra186, change the prefix from TEGRA_ to TEGRA186_. Note that for now we need to keep the old definitions in place to avoid breaking compilation in file that use this header. Once all users have been converted to use the new defines, the old ones can be removed. Also note that this is only a naming change and doesn't affect device tree ABI. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-12-05clk: qcom: gcc-msm8998: Add clkref clocksBjorn Andersson
Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: qcom: Enumerate remaining msm8998 resetsJeffrey Hugo
The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05soc: imx: gpcv2: add support for i.MX8MQ SoCLucas Stach
The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-04clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) added the CPEX clock on R-Car D3. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Add the missing clock to the DT bindings header, and implement support for it in the clock driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Dec 22, 2017, and Feb 28, 2018) removed the SSPSRC, SSP1, and SSP2 clocks on R-Car D3, as this SoC does not have a Stream and Security Processor. As these definitions were never used, they can just be removed. The freed slots in the DT bindings header must not be reused, though. Fixes: 714c53aa2e2d6d60 ("clk: renesas: Add r8a77995 CPG Core Clock Definitions") Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04dt-bindings: clock: r8a7796: Remove CSIREF clockGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.52 (Nov 30, 2016) removed the CSI reference clock on R-Car M3-W. As this definition was never used, it can just be removed. The freed slot in the DT bindings header must not be reused, though. Fixes: 972610fb23b08dd5 ("clk: renesas: Add r8a7796 CPG Core Clock Definitions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04dt-bindings: clock: r8a7795: Remove CSIREF clockGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.52 (Nov 30, 2016) removed the CSI reference clock on R-Car H3. As this definition was never used, it can just be removed. The freed slot in the DT bindings header must not be reused, though. Fixes: 9d0c3c682033d3f1 ("clk: shmobile: Add r8a7795 CPG Core Clock Definitions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04dt-bindings: clock: Add Allwinner suniv F1C100s CCUMesih Kilinc
Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-03Merge tag 'arm-soc/for-4.21/drivers' of https://github.com/Broadcom/stblinux ↵Olof Johansson
into next/drivers This pull request contains Broadcom ARM/ARM64/MIPS SoCs drivers changes for 4.21, please pull the following changes: - James fixes the firmware interface after a commit changed the use of VLA and broke large transfers - Stefan adds a timeout check for Raspberry Pi firmware transactions and updates a bunch of SoC/firmware files to use SPDX tags - Wolfram switches the GISB bus arbiter to use dev_get_drvdata() - Yangtao provides a fix for a reference leak due to a call to of_find_node_by_path() - Florian fixes the CPU re-entry point out of S3 suspend with kernels built in Thumb2 mode * tag 'arm-soc/for-4.21/drivers' of https://github.com/Broadcom/stblinux: soc: bcm: brcmstb: Don't leak device tree node reference firmware: raspberrypi: Switch to SPDX identifier firmware: raspberrypi: Fix firmware calls with large buffers soc: bcm: Switch raspberrypi-power to SPDX identifier firmware: raspberrypi: Define timeout for transactions bus: brcmstb_gisb: simplify getting .driver_data soc: bcm: brcmstb: Fix re-entry point with a THUMB2_KERNEL Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03dt-bindings: clock: add imx7ulp clock binding docA.s. Dong
i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03media: xilinx: Use SPDX-License-IdentifierDhaval Shah
SPDX-License-Identifier is used for the Xilinx Video IP and related drivers. [Added drivers/media/platform/xilinx/Kconfig] [Added drivers/media/platform/xilinx/Makefile] [Added include/dt-bindings/media/xilinx-vip.h] Signed-off-by: Dhaval Shah <dhaval23031987@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-12-03dt-bindings: Add binding for i.MX8MQ CCMLucas Stach
This adds the binding for the i.MX8MQ Clock Controller Module. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03dt-bindings: clock: Introduce QCOM LPASS clock bindingsTaniya Das
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-30soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchyGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A3VIP power domain on R-Car V3H to A3VIP0, and clarified the power domain hierarchy for the A3VIP[012] power domains. As the definition for the A3VIP0 domain is not yet used from DT, it can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domainsGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A2PD0 and A2DP0 power domains on R-Car V3H to A2DP0 resp. A2DP1. As these definitions are not yet used from DT, they can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domainsGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A2IR2 and A2IR3 power domains on R-Car V3M to A2DP resp. A2CN. As these definitions are not yet used from DT, they can just be renamed. While at it, fix the indentation of the A3IR definition. Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domainGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) removed the CR7 power domain on R-Car V3M, as this SoC does not have an ARM Cortex-R7 Realtime Core. As this definition was never used from DT, it can just be removed. Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-29clk: mediatek: add clock support for MT7629 SoCRyder Lee
Add all supported clocks exported from every susbystem found on MT7629 SoC. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-27dt-bindings: clock: Introduce QCOM Graphics clock bindingsAmit Nischal
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Add input clocks property] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-27dt-bindings: thermal: tegra-bpmp: Add Tegra194 supportThierry Reding
The thermal controller implementation on Tegra194 is very similar to the implementation on Tegra186. Add a compatible string for the new generation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-26Merge branch 'v4.21-shared/clkids' into v4.21-clk/nextHeiko Stuebner
2018-11-26clk: rockchip: add clock ID of ACODEC for rk3328Katsuhiro Suzuki
This patch adds clock ID of audio CODEC (ACODEC) for rk3328. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-25Merge tag 'sh-pfc-for-v4.21-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.21 - Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W, - Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C, - Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3, - Add QSPI pin groups on R-Car V3M and V3H, - Add VIN and CAN(FD) pin groups on R-Car M3-N, - Add I2C[035] pin groups on R-Car H3 and M3-W, - Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC, - Small cleanups, - Maintainership updates.
2018-11-24dt-bindings: dmaengine: dw-dmac: add protection control propertyChristian Lamparter
This patch for the DesignWare AHB Central Direct Memory Access Controller adds the dma protection control property: "snps,dma-protection-control" as well as the properties specific values defines into a new include file: include/dt-bindings/dma/dw-dmac.h Note: The protection control signals are one-to-one mapped to the AHB HPROT[1:3] signals for this controller. The HPROT0 (Data Access) is always hardwired to 1. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-23dt-bindings: clk: meson-gxbb: Add Video clock bindingsNeil Armstrong
Add the video clock bindings covering all the video graphics pipeline and the HDMI controller. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: http://lkml.kernel.org/r/1541516257-16157-4-git-send-email-narmstrong@baylibre.com
2018-11-23dt-bindings: clock: meson8b: export the CPU post dividersMartin Blumenstingl
There are four CPU clock post dividers: - ABP - PERIPH (used as input for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Export these so we can use them in .dts files. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181122214017.25643-2-martin.blumenstingl@googlemail.com
2018-11-23dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIOChris Brandt
Add device tree binding documentation and header file for Renesas R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328Katsuhiro Suzuki
This patch fixes mistakes in HCLK_I2S1_8CH for running I2S1 successfully. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-16pinctrl: bcm2835: Switch to SPDX identifierStefan Wahren
Adopt the SPDX license identifier headers to ease license compliance management. Cc: Simon Arlott <simon@arlott.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-15dt-bindings: marvell,mmp2: Add clock id for the SP clockLubomir Rintel
This is the clock for the "security processor" core. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2018-11-15dt-bindings: pinctrl: Add devicetree bindings for MT6797 SoC PinctrlManivannan Sadhasivam
Add devicetree bindings for Mediatek MT6797 SoC Pin Controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-14clk: bcm2835: Switch to SPDX identifierStefan Wahren
Adopt the SPDX license identifier headers to ease license compliance management. Cc: Simon Arlott <simon@arlott.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-14soc: bcm: Switch raspberrypi-power to SPDX identifierStefan Wahren
Adopt the SPDX license identifier headers to ease license compliance management. Cc: Alexander Aring <aring@mojatatu.com> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-14dt-bindings: imx: add scu resource id headfileA.s. Dong
SCU firmware uses resource id to provide services. Every device on a SCU based system has a resource id. Exported it in device tree to allow service bindings to use it. e.g. power domain. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-06clk: qcom: smd: Add support for QCS404 rpm clocksTaniya Das
Add rpm smd clocks, PMIC and bus clocks which are required on QCS404 for clients to vote on. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> [bjorn: Dropped cxo, voter clocks and static initialization] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 15:28:39 +0000