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2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' ↵Stephen Boyd
and 'clk-debugfs-simple' into clk-next * clk-imx7d: clk: imx7d: reset parent for mipi csi root clk: imx7d: fix mipi dphy div parent * clk-hisi-stub: clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB * clk-mvebu: clk: mvebu: use correct bit for 98DX3236 NAND * clk-imx6-epit: clk: imx6: add EPIT clock support * clk-debugfs-simple: clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions
2018-06-04Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-nextStephen Boyd
* clk-imx6sx: clk: imx6sl: correct ocram_podf clock type clk: imx6sx: disable unnecessary clocks during clock initialization clk: imx6sx: add missing lvds2 clock to the clock tree * clk-imx7d-enet: ARM: dts: imx7: correct enet ipg clock clk: imx7d: correct enet clock CCGR registers clk: imx7d: correct enet phy ref clock gates * clk-aspeed-24: clk: aspeed: Add 24MHz fixed clock
2018-06-04Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' ↵Stephen Boyd
and 'clk-qcom-mmagic' into clk-next * clk-allwinner: clk: sunxi-ng: r40: export a regmap to access the GMAC register clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: add support for H6 PRCM CCU * clk-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper * clk-tegra: clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra20: Add DEV1/DEV2 OSC dividers * clk-berlin: clk: berlin: switch to SPDX license identifier * clk-qcom-mmagic: clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled clk: qcom: Register the gdscs before the clocks clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
2018-06-04Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', ↵Stephen Boyd
'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next * clk-hisi-usb: clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC * clk-silent-bulk: clk: bulk: silently error out on EPROBE_DEFER * clk-mtk-hdmi: clk: mediatek: correct the clocks for MT2701 HDMI PHY module * clk-mtk-mali: clk: mediatek: add g3dsys support for MT2701 and MT7623 dt-bindings: reset: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add g3dsys bindings * clk-imx6ul-ccosr: clk: imx: Add new clo01 and clo2 controlled by CCOSR
2018-06-04Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', ↵Stephen Boyd
'clk-stratix10' and 'clk-aspeed' into clk-next * clk-stm32mp1: clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()' clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock clk: stm32mp1: remove ck_apb_dbg clock clk: stm32mp1: set stgen_k clock as critical clk: stm32mp1: add missing tzc2 clock clk: stm32mp1: fix SAI3 & SAI4 clocks clk: stm32mp1: remove unused dfsdm_src[] const clk: stm32mp1: add missing static * clk-samsung: clk: samsung: simplify getting .drvdata * clk-uniphier-mpeg: clk: uniphier: add LD11/LD20 stream demux system clock * clk-stratix10: clk: socfpga: stratix10: suppress unbinding platform's clock driver clk: socfpga: stratix10: use platform driver APIs * clk-aspeed: clk:aspeed: Fix reset bits for PCI/VGA and PECI clk: aspeed: Support second reset register
2018-06-04Merge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and ↵Stephen Boyd
'clk-qcom-rcg-fix' into clk-next * clk-qcom-rpmh: dt-bindings: clock: Introduce QCOM RPMh clock bindings * clk-npcm7xx: clk: npcm7xx: fix return value check in npcm7xx_clk_init() clk: npcm7xx: add clock controller dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock * clk-of-parent-count: pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding clk: Extract OF clock helpers in <linux/of_clk.h> * clk-qcom-rcg-fix: clk: qcom: Base rcg parent rate off plan frequency
2018-06-04Merge branch 'clk-actions' into clk-nextStephen Boyd
* clk-actions: clk: actions: Add S900 SoC clock support clk: actions: Add pll clock support clk: actions: Add composite clock support clk: actions: Add fixed factor clock support clk: actions: Add factor clock support clk: actions: Add divider clock support clk: actions: Add mux clock support clk: actions: Add gate clock support clk: actions: Add common clock driver support dt-bindings: clock: Add Actions S900 clock bindings
2018-06-01dt-bindings: clk: Update Stingray binding docPramod Kumar
Update Stingray clock binding document to add additional clock entries with names matching the latest ASIC datasheet. Also modify a few existing entries to make their naming more consistent with the rest of the entries Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: imx6: add EPIT clock supportColin Didier
Add EPIT clock support to the i.MX6Q clocking infrastructure. Signed-off-by: Colin Didier <colin.didier@devialet.com> Signed-off-by: Clément Peron <clement.peron@devialet.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: aspeed: Add 24MHz fixed clockLei YU
Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by: Lei YU <mine260309@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: imx7d: correct enet clock CCGR registersAnson Huang
Correct enet clock gates as below: CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK Just rename unused IMX7D_ENETx_REF_ROOT_CLK for IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01dt-bindings: clock: Introduce QCOM Video clock bindingsAmit Nischal
Add device tree bindings for video clock controller for Qualcomm Technology Inc's SoCs. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-30ASoC: imx-audmux: add RXFS/RXCLK defines for 6-wire connectionsPhilipp Zabel
In asynchronous mode, a RxFS and RxClk connection needs to be made between two ports. Add a define for the bit to be set in the *SEL fields. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [m.felsch@pengutronix.de: fixed comment to include i.MX21 and 35] Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-29ASoC: qdsp6: dt-bindings: Add q6afe tdm dt bindingSrinivas Kandagatla
This patch adds bindings required for TDM ports on AFE. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-26Merge tag 'renesas-soc-for-v4.18' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Renesas ARM Based SoC Updates for v4.18 * SoC - Change platform dependency to ARCH_RENESAS This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near future. - Add the to Kconfig RZ/N1D (r9a06g032) SoC - Identify R-Car E3 (r8a77990) SoC - Identify and add minimal support for RZ/G1C (r8a77470) SoC * R-Car SYSC - Add support for R-Car E3 (r8a77990) SoC - Remove unused inclusion of <linux/sys_soc.h>, - Make r8a77995_areas[] const. * R-Car Reset - Add support for R-Car E3 (r8a77990) SoC * Debug-LL - Add support for RZ/G1C (r8a77470) SoC * tag 'renesas-soc-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B} soc: renesas: rcar-sysc: Add support for R-Car E3 power areas arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig arm: shmobile: Change platform dependency to ARCH_RENESAS soc: renesas: r8a77995-sysc: Cleanups soc: renesas: rcar-rst: Add support for R-Car E3 soc: renesas: Add r8a77990 SYSC PM Domain Binding Definitions soc: renesas: identify R-Car E3 ARM: debug-ll: Add support for r8a77470 ARM: shmobile: Add the RZ/N1 arch to the shmobile Kconfig ARM: shmobile: r8a77470: basic SoC support soc: renesas: rcar-sysc: Add r8a77470 support soc: renesas: rcar-rst: Add support for RZ/G1C soc: renesas: Identify RZ/G1C Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-25Merge tag 'v4.18-rockchip-drivers-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Power-domain support for Rockchip socs px30, rk3128, rk3228 and rk3036. * tag 'v4.18-rockchip-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: power-domain: add power domain support for px30 dt-bindings: power: add binding for px30 power domains dt-bindings: power: add PX30 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3228 dt-bindings: power: add binding for rk3228 power domains dt-bindings: power: add RK3228 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3128 dt-bindings: power: add binding for rk3128 power domains dt-bindings: power: add RK3128 SoCs header for power-domain soc: rockchip: power-domain: add power domain support for rk3036 dt-bindings: power: add binding for rk3036 power domains dt-bindings: power: add RK3036 SoCs header for power-domain Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-25Merge tag 'phy-for-4.18' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.18 *) Add PHY driver for the ATH79 USB PHY *) Add USB3 PHY driver for Mediatek XS-PHY *) Add QUSB/QMP V3 USB3 PHY Support for Qualcomm's SDM845 *) Add runtime PM support for mapphone PHY driver *) Allow phy_pm_runtime_xxx API calls to accept NULL *) Other minor cleanups and fixes Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-25Merge tag 'tegra-for-4.18-memory-v2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers memory: tegra: Changes for v4.18-rc1 This contains some cleanup of the memory controller driver as well as unification work to share more code between Tegra20 and later SoC generations. Also included are an implementation for the hot resets functionality by the memory controller which is required to properly reset busy hardware. * tag 'tegra-for-4.18-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Register SMMU after MC driver became ready memory: tegra: Add Tegra210 memory controller hot resets memory: tegra: Add Tegra124 memory controller hot resets memory: tegra: Add Tegra114 memory controller hot resets memory: tegra: Add Tegra30 memory controller hot resets memory: tegra: Add Tegra20 memory controller hot resets memory: tegra: Introduce memory client hot reset memory: tegra: Squash tegra20-mc into common tegra-mc driver memory: tegra: Remove unused headers inclusions memory: tegra: Apply interrupts mask per SoC memory: tegra: Setup interrupts mask before requesting IRQ memory: tegra: Do not handle spurious interrupts dt-bindings: memory: tegra: Add hot resets definitions Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-23dt-bindings: power: add PX30 SoCs header for power-domainFinley Xiao
According to a description from TRM, add all the power domains. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23dt-bindings: power: add RK3228 SoCs header for power-domainElaine Zhang
According to a description from TRM, add all the power domains. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23dt-bindings: power: add RK3128 SoCs header for power-domainElaine Zhang
According to a description from TRM, add all the power domains. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23dt-bindings: power: add RK3036 SoCs header for power-domainCaesar Wang
According to a description from TRM, add all the power domains. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-20dt-bindings: phy-qcom-usb2: Add support to override tuning valuesManu Gautam
To improve eye diagram for PHYs on different boards of same SOC, some parameters may need to be changed. Provide device tree properties to override these from board specific device tree files. While at it, replace "qcom,qusb2-v2-phy" with compatible string for USB2 PHY on sdm845 which was earlier added for sdm845 only. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-18dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitionsDmitry Osipenko
Tegra114 doesn't have SATA nor PCIe, but TRM seems erroneously document them. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-15clk: imx: Add new clo01 and clo2 controlled by CCOSRMichael Trimarchi
osc->cko2_sel->cko2_podf->clk_cko2->clk_cko Example of usage to provide clock to the sgtl5000 codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6UL_CLK_OSC>; #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_CKO>; assigned-clocks = <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>, <&clks IMX6UL_CLK_CKO>; assigned-clock-parents = <&clks IMX6UL_CLK_OSC>, <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>; clock-names = "mclk"; wlf,shared-lrclk; Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Tested-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15dt-bindings: reset: mediatek: add entry for Mali-450 node to referSean Wang
Just add binding for a required reset referenced by Mali-450 on MT7623 or MT2701 SoC. Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15dt-bindings: clock: mediatek: add entry for Mali-450 node to referSean Wang
Just add binding for a required clock referenced by Mali-450 on MT7623 or MT2701 SoC. Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee
The hdmitx_dig_cts clock signal is not a child of clk26m, and the actual output of the PLL block is derived from the tvdpll via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoCJianguo Sun
There are two USB3 host controllers on Hi3798CV200 SoC. This commit adds missing clocks for them. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15clk:aspeed: Fix reset bits for PCI/VGA and PECIJae Hyun Yoo
This commit fixes incorrect setting of reset bits for PCI/VGA and PECI modules. 1. Reset bit for PCI/VGA is 8. 2. PECI reset bit is missing so added bit 10 as its reset bit. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Cc: stable <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15clk: aspeed: Support second reset registerJoel Stanley
The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15dt-bindings: clock: reset: Add AXG AO Clock and Reset BindingsYixun Lan
Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
The bpf syscall and selftests conflicts were trivial overlapping changes. The r8169 change involved moving the added mdelay from 'net' into a different function. A TLS close bug fix overlapped with the splitting of the TLS state into separate TX and RX parts. I just expanded the tests in the bug fix from "ctx->conf == X" into "ctx->tx_conf == X && ctx->rx_conf == X". Signed-off-by: David S. Miller <davem@davemloft.net>
2018-05-11ASoC: qdsp6: dt-bindings: Add q6asm dt bindingsSrinivas Kandagatla
This patch add DT bindings for ASM (Audio Stream Manager) DSP module. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-and-tested-by: Rohit kumar <rohitkr@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-11ASoC: qdsp6: dt-bindings: Add q6afe dt bindingsSrinivas Kandagatla
This patch add DT bindings for AFE (Audio Frontend) DSP module. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-and-tested-by: Rohit kumar <rohitkr@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-11soc: qcom dt-bindings: Add APR bus bindingsSrinivas Kandagatla
This patch add dt bindings for Qualcomm APR (Asynchronous Packet Router) bus driver. This bus is used for communicating with DSP which provides audio and various other services to cpu. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-11ASoC: rt5640: Add devicetree-bindings for dmic, jack-detectHans de Goede
Add devicetree-bindings for the dmic, jack-detect source and overcurrent- detect threshold settings. The dmic bindings mirror the existing bindings for the rt5645. The jd-src and ovcd bindings mirror the existing bindings for the rt5651. Cc devicetree@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-08clk: qcom: Add DT bindings for SDM845 gcc clock controllerAmit Nischal
Add compatible string and the include file for gcc clock controller for SDM845. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-04clk: imx6sx: add missing lvds2 clock to the clock treeAnson Huang
i.MX6SX has lvds2 (analog clock2), an I/O clock like lvds1. And this lvds2, along with lvds1, can be used to provide external clock source to the internal pll, such as pll4_audio and pll5_video. This patch mainly adds the lvds2 to the clock tree and fix its relationship with pll accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-04clk: sunxi-ng: add support for H6 PRCM CCUIcenowy Zheng
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3 and A64. However, the PRCM CCU is rearranged; the register arragement is now similar to the main CCU of H6, and the PRCM now has two APB buses to control -- one is clocked from AHB clock derivde from AR100 clock, the other is clocked from the same mux with AR100 clock. Therefore a new driver is written for it. As there's no official document about the PRCM in H6, all the information are indirectly collected from BSP and parts of the document, and the information source is noted as comments in the driver's source code. If reliable information is provided furtherly, the driver needs to be rechecked. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-05-02dt-bindings: clock: Introduce QCOM RPMh clock bindingsTaniya Das
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These devices would be used for communicating resource state requests to control the clocks managed by RPMh. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-02MIPS: dts: jz4780: Add DMA controller node to the devicetreeEzequiel Garcia
Add the devicetree node to support the DMA controller found in JZ480 SoCs. Tested-by: Mathieu Malaterre <malat@debian.org> Acked-by: James Hogan <jhogan@kernel.org> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-02pinctrl: mediatek: update pinmux defintions for MT7623Ryder Lee
Fulfill the pinmux macros for MT7623 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-04-27dt-bindings: memory: tegra: Add hot resets definitionsDmitry Osipenko
Add definitions for the Tegra20+ memory controller hot resets. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-04-25clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocksMaxime Jourdan
Export video decoder clock dt-bindings Signed-off-by: Maxime Jourdan <maxi.jourdan@wanadoo.fr> [added commit description] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-04-25dt-bindings: clock: meson8b: export the NAND clockMartin Blumenstingl
Export the NAND clock to the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-04-24clk: renesas: Add r8a77990 CPG Core Clock DefinitionsTakeshi Kihara
This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs. Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, POST3) are not included, as they are used as internal clock sources only, and never referenced from DT. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [shimoda: add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-04-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
Conflicts were simple overlapping changes in microchip driver. Signed-off-by: David S. Miller <davem@davemloft.net>
2018-04-20lan78xx: Read LED states from Device TreePhil Elwell
Add support for DT property "microchip,led-modes", a vector of zero to four cells (u32s) in the range 0-15, each of which sets the mode for one of the LEDs. Some possible values are: 0=link/activity 1=link1000/activity 2=link100/activity 3=link10/activity 4=link100/1000/activity 5=link10/1000/activity 6=link10/100/activity 14=off 15=on These values are given symbolic constants in a dt-bindings header. Also use the presence of the DT property to indicate that the LEDs should be enabled - necessary in the event that no valid OTP or EEPROM is available. Signed-off-by: Phil Elwell <phil@raspberrypi.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-04-16clk: qcom: Add MSM8998 Global Clock Control (GCC) driverJoonwoo Park
Add support for the global clock controller found on MSM8998 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Specify regs for alpha_plls, fix white spaces and add binding] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 10:15:49 +0000