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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.15
1. Google GS101:
- Disable GSA core pinctrl because its registers are not available for
normal world.
- Add APM (Active Power Management) mailbox and the ACPM firmware nodes.
- Add new boards: Google Pixel 6 Pro (Raven).
- Enable framebuffer and reboot-mode.
2. Exynos990:
- Add PERIS clock controller, MCT timer
3. Exynos8895:
- Define all remaining serial engine (USI) and syscon nodes, add MMC.
- Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte).
4. ExynosAutov920: Add UFS and CPU cache information.
5. Various cleanups.
This includes two topic branches with DT bindings, which might be shared
with other trees depending on needs:
1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller
header constants.
2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines
header constants rework.
* tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits)
arm64: dts: tesla: Change labels to lower-case
arm64: dts: exynos: gs101: Change labels to lower-case
arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
arm64: dts: exynosautov920: add CPU cache information
arm64: dts: exynos: gs101: add ACPM protocol node
arm64: dts: exynos: gs101: add AP to APM mailbox node
arm64: dts: exynos: gs101: add SRAM node
arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
arm64: dts: exynos: gs101: align poweroff writes with downstream
arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes
arm64: dts: exynos8895: Rename PMU nodes to fixup sorting
arm64: dts: exynos8895-dreamlte: enable support for the touchscreen
arm64: dts: exynos8895-dreamlte: enable support for microSD storage
arm64: dts: exynos8895: add a node for mmc
arm64: dts: exynos8895: define all usi nodes
arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1
arm64: dts: exynos990: Rename and sort PMU nodes
arm64: dts: exynos990: Add CMU_PERIS and MCT nodes
dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi
dt-bindings: clock: exynos990: Add CMU_PERIS block
...
Link: https://lore.kernel.org/r/20250309185601.10616-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: MNT-Reform2 laptop (rk3588), OrangePi5-Ultra (rk3588),
Radxa Rock 4D (rk3576), Firefly ROC-RK3576-PC, Photonicat (rk3568)
New overlays: Video-adapters for Theobroma boards and one adapter used
in hw test scenarios.
Interesting bigger changes contain clock support for rk3528; support for
the hdmi1 controller as well as hdmi-audio support on both controllers on
rk3588; the hdmi-receiver of the rk3588 landed, and rk3576 got basic
graphics support and can now do hdmi output.
Another big block is that we're now doing overlays way better and are
including build-testing for applied overlays to the base dtb - similar
to how other arches already do this.
Of cours a big list of more controllers for rk3576 (nvmem, sfc), rk3588
(rng, spdif, regulator for gpu power-domain) and rk3528 (saradc, pinctrl)
And a huge number of board-level improvements and additions.
* tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (89 commits)
arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D
arm64: dts: rockchip: Add SFC nodes for rk3576
arm64: dts: rockchip: Add maskrom button to Radxa E20C
arm64: dts: rockchip: Add SARADC node for RK3528
arm64: dts: rockchip: Add user button to Radxa E20C
arm64: dts: rockchip: Add leds node to Radxa E20C
arm64: dts: rockchip: Add HDMI support for rock-4d
arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
arm64: dts: rockchip: Enable HDMI receiver on rock-5b
arm64: dts: rockchip: Add device tree support for HDMI RX Controller
arm64: dts: rockchip: Add rk3528 QoS register node
dt-bindings: mfd: syscon: Add rk3528 QoS register compatible
arm64: dts: rockchip: add MNT Reform 2 laptop
dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE)
dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon
dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon
arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10
arm64: dts: rockchip: Enable hdmi display on sige5
arm64: dts: rockchip: Add hdmi for rk3576
arm64: dts: rockchip: Add vop for rk3576
...
Link: https://lore.kernel.org/r/13791512.uLZWGnKmhe@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for
the main and the PRCM R-CCU.
The source clock list differs in some annoying details, and folding this
into the existing Allwinner CCU clock binding document gets quite
unwieldy, so create a new document for these CCUs.
Add the new compatible string, along with the required input clock
lists. This conditionally describes the input clock lists, to make
adding support for the other two CCUs easier.
Also add the DT binding headers, listing all the clocks with their ID
numbers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI. Document the devicetree bindings as well.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250301-exynos7870-pmu-clocks-v5-1-715b646d5206@disroot.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Provide dt-schema documentation for Exynos2200 SoC clock controller.
Add device tree clock binding definitions for the following CMU blocks:
- CMU_ALIVE
- CMU_CMGP
- CMU_HSI0
- CMU_PERIC0/1/2
- CMU_PERIS
- CMU_TOP
- CMU_UFS
- CMU_VTS
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250223115601.723886-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Document the device tree bindings of the rockchip rk3562 SoC
clock and reset unit.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250227105916.2340856-2-kever.yang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add binding for the HDMI TX clock found in the VDO1 controller.
While at it, also remove the unused CLK_VDO1_NR_CLK.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250212100342.33618-1-angelogioacchino.delregno@collabora.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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DSI phys, from earliest (28 nm) up to newest (3 nm) generation, provide
two clocks. The respective clock ID is used by drivers and DTS, so it
should be documented as explicit ABI.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/634146/
Link: https://lore.kernel.org/r/20250127132105.107138-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Add the required clock and reset bindings for the LCD TCON.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250213172248.158447-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
on these new introduced constants so consumer nodes can easily use the
correct one in DTS files matching properly what is being used in driver
code (clock IDs are implicitly used there).
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Firmware contants do not fit the purpose of bindings because they are not
independent IDs for abstractions. They are more or less just contants which
better to wire via header with DT which is using it.
That's why add deprecated message to dt binding header and also update
existing dt bindings not to use macros from the header and replace them by
it's value. Actually value is not relevant because it is only example.
The similar changes have been done by commit 9d9292576810 ("dt-bindings:
pinctrl: samsung: deprecate header with register constants").
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2a6f0229522327939e6893565e540b75f854a37b.1738600745.git.michal.simek@amd.com
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into clk-for-6.15
Merge the QCS8300 multimedia clock controllers through a topic branch,
to make binding constants available to DeviceTree source as well.
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The QCS8300 camera clock controller is a derivative of SA8775P, but has
an additional clock and minor differences. Hence, reuse the SA8775P
camera bindings and add additional clock required for QCS8300.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, reuse gpucc bindings of
SA8775P and add additional clocks required for QCS8300.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add resets for eMMC/SD card blocks that were missed during initial
driver submission.
Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250203063427.358327-2-alexeymin@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document the qcom,rpmcc-sdm429 compatible and
add BB_CLK3 clock definition.
Signed-off-by: Daniil Titov <daniilt971@gmail.com>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250212-sdm429-rpm-v1-1-0a24ac19a478@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add missing clock IDs for the CIF (Camera InterFace) blocks
on the RK3188/RK3066.
Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241205182954.5346-1-val@packett.cool
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add CMU_PERIS block compatible, and clock definitions.
CMU_PERIS requires one bus clock dependency, and it's used for i.e the MCT.
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250104-exynos990-cmu-v1-1-9f54d69286d6@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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The QCS8300 camera clock controller is a derivative of SA8775P, but has
an additional clock and minor differences. Hence, reuse the SA8775P
camera bindings and add additional clock required for QCS8300.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, reuse gpucc bindings of
SA8775P and add additional clocks required for QCS8300.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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'clk-bcm' into clk-next
* clk-airoha:
clk: en7523: Add clock for eMMC for EN7581
dt-bindings: clock: add ID for eMMC for EN7581
dt-bindings: clock: drop NUM_CLOCKS define for EN7581
clk: en7523: Rework clock handling for different clock numbers
clk: en7523: Initialize num before accessing hws in en7523_register_clocks()
clk: en7523: Fix wrong BUS clock for EN7581
clk: amlogic: axg-audio: revert reset implementation
Revert "clk: Fix invalid execution of clk_set_rate"
* clk-rockchip:
clk: rockchip: rk3588: make refclko25m_ethX critical
clk: rockchip: rk3588: drop RK3588_LINKED_CLK
clk: rockchip: implement linked gate clock support
clk: rockchip: expose rockchip_clk_set_lookup
clk: rockchip: rk3588: register GATE_LINK later
clk: rockchip: support clocks registered late
* clk-stm:
clk: stm32f4: support spread spectrum clock generation
clk: stm32f4: use FIELD helpers to access the PLLCFGR fields
dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking
dt-bindings: clock: convert stm32 rcc bindings to json-schema
* clk-thead:
clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks
clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot
clk: thead: Fix clk gate registration to pass flags
* clk-bcm:
clk: bcm: rpi: Add disp clock
clk: bcm: rpi: Create helper to retrieve private data
clk: bcm: rpi: Enable minimize for all firmware clocks
clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks
clk: bcm: rpi: Add ISP to exported clocks
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'clk-qcom' into clk-next
* clk-microchip:
clk: at91: sama7d65: add sama7d65 pmc driver
dt-bindings: clock: Add SAMA7D65 PMC compatible string
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks
dt-bindings: clk: at91: Add clock IDs for the slow clock controller
* clk-xilinx:
clk: clocking-wizard: calculate dividers fractional parts
dt-bindings: clock: xilinx: Add reset GPIO for VCU
dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
* clk-allwinner:
clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
* clk-imx:
clk: imx: Apply some clks only for i.MX93
arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
dt-bindings: clock: imx93: Add SPDIF IPG clk
clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
clk: imx8mp: Fix clkout1/2 support
* clk-qcom: (63 commits)
clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
dt-bindings: clock: move qcom,x1e80100-camcc to its own file
clk: qcom: smd-rpm: Add clocks for MSM8940
dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
clk: qcom: smd-rpm: Add clocks for MSM8937
dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
dt-bindings: interconnect: Add Qualcomm IPQ5424 support
clk: qcom: Add SM6115 LPASSCC
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
clk: qcom: gcc-sdm845: Add general purpose clock ops
clk: qcom: clk-rcg2: split __clk_rcg2_configure function
clk: qcom: clk-rcg2: document calc_rate function
clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
clk: qcom: ipq5424: add gcc_xo_clk
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
clk: qcom: ipq5424: remove apss_dbg clock
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
...
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and 'clk-socfpga' into clk-next
- Support for 5L35023 variant of Versa 3 clock generator
* clk-cleanup:
clk: analogbits: Fix incorrect calculation of vco rate delta
clk: Use str_enable_disable-like helpers
clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()
clk: starfive: Make _clk_get become a common helper function
clk: ep93xx: make const read-only arrays static
clk: lmk04832: make read-only const arrays static
clk: ti: use kcalloc() instead of kzalloc()
dt-bindings: clock: st,stm32mp1-rcc: complete the reference path
dt-bindings: clock: st,stm32mp1-rcc: fix reference paths
dt-bindings: clock: ti: Convert composite.txt to json-schema
dt-bindings: clock: ti: Convert gate.txt to json-schema
clk: Drop obsolete devm_clk_bulk_get_all_enable() helper
PCI: exynos: Switch to devm_clk_bulk_get_all_enabled()
soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled()
clk: davinci: remove platform data struct
clk: fix an OF node reference leak in of_clk_get_parent_name()
clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check
clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check
clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check
* clk-renesas: (24 commits)
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
clk: versaclock3: Add support for the 5L35023 variant
dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
clk: versaclock3: Prepare for the addition of 5L35023 device
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
clk: renesas: r8a779h0: Add display clocks
clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
clk: renesas: rzv2h: Add selective Runtime PM support for clocks
clk: renesas: r9a06g032: Use BIT macro consistently
...
* clk-mediatek:
clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883
clk: mediatek: mt2701-img: add missing dummy clk
clk: mediatek: mt2701-mm: add missing dummy clk
clk: mediatek: mt2701-bdp: add missing dummy clk
clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe
clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe
* clk-samsung:
clk: samsung: Introduce Exynos990 clock controller driver
clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}
dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
* clk-socfpga:
clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
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The patch converts st,stm32-rcc.txt to the JSON schema, but it does more
than that. The old bindings, in fact, only covered the stm32f{4,7}
platforms and not the stm32h7. Therefore, to avoid patch submission tests
failing, it was necessary to add the corresponding compatible (i. e.
st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead
of the 2 required for the stm32f{4,7} platforms.
Additionally, the old bindings made no mention of the st,syscfg property,
which is used by both the stm32f{4,7} and the stm32h7 platforms.
The patch also fixes the files referencing to the old st,stm32-rcc.txt.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add ID for eMMC for EN7581. This is to control clock selection of eMMC
between 200MHz and 150MHz.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250113231030.6735-4-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Drop NUM_CLOCKS define for EN7581 include. This is not a binding and
should not be placed here. Value is derived internally in the user
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250113231030.6735-3-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.
Add bindings for it.
Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[alexey.klimov slightly changed the commit message]
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org
[bjorn: Adjusted Konrad's address]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the missing "RENESAS" part to the include guard.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/34953d1e9f472e4f29533ed06cf092dd3c0d1178.1736238939.git.geert+renesas@glider.be
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The GCC_XO_CLK is required for the functionality of the WiFi
copy engine block. Therefore, add the GCC_XO_CLK macro.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241210064110.130466-2-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The gcc_apss_dbg clk is access protected by trust zone, and accessing
it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk macro.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20241217113909.3522305-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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APQ8064 / MSM8960 have separate LVDS / LCDC clock, driving the MDP4 LCD
controller. Add corresponding indices to clock controller bindings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-2-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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clk-for-6.14
Merge the IPQ CMN PLL clock binding through a topic branch to make it
available to DeviceTree source branches as well.
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The CMN PLL controller provides clocks to networking hardware blocks
and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
on-chip Wi-Fi, and produces output clocks at fixed rates. These output
rates are predetermined, and are unrelated to the input clock rate.
The primary purpose of CMN PLL is to supply clocks to the networking
hardware such as PPE (packet process engine), PCS and the externally
connected switch or PHY device. The CMN PLL block also outputs fixed
rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
clock supplied to GCC.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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clk-for-6.14
Merge SM8750 display clock controller bindings through topic branch, to
make available to DeviceTree source branch as well.
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Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC).
Bindings are similar to existing SM8550 and SM8650 (same clock inputs),
but the clock hierarchy is quite different and these are not compatible
devices.
The binding header was copied from downstream sources, so I retained
original copyrights.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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into clk-for-6.14
Merge the SM8750 GCC and TCSR clock bindings through topic branch, to
allow merging into DeviceTree source branch as well.
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Add bindings documentation for the SM8750 Clock Controller.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add device tree bindings for the global clock controller on Qualcomm
SM8750 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Export PLL_VIDEO_2X and PLL_MIPI, these will be used to explicitly
select TCON0 clock parent in dts
Fixes: ca1170b69968 ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux")
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Frank Oltmanns <frank@oltmanns.dev> # on PinePhone
Tested-by: Stuart Gathman <stuart@gathman.org> # on OG Pinebook
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://patch.msgid.link/20250104074035.1611136-2-anarsoul@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add SPDIF IPG clk. The SPDIF IPG clock and root clock
share same clock gate.
Fixes: 1c4a4f7362fd ("arm64: dts: imx93: Add audio device nodes")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241119015805.3840606-2-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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into clk-for-6.14
Merge the X1P42100 GPUCC binding through a topic branch to make
available for the DeviceTree branch as well.
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To make it easier for X1P4 and X1E to share a common device tree base,
extend the existing latter's GPUCC bindings and reuse them on the
former platform.
While not in the same file, it only makes sense to introduce the new
compatible in this commit as well.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the `microchip,sama7d65-pmc` compatible string to the existing binding,
since the SAMA7D65 PMC shares the same properties and clock requirements
as the SAMA7G5.
Export MCK3 and MCK5 to be accessed and referenced in DT to assign to
the clocks property for sama7d65 SoC.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/5252a28531deaee67af1edd8e72d45ca57783464.1733505542.git.Ryan.Wanner@microchip.com
[claudiu.beznea: use tabs instead of spaces in
include/dt-bindings/clock/at91.h]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Add dt-schema documentation for the Exynos990 SoC CMU.
This clock management unit has a topmost block (CMU_TOP)
that generates top clocks for other blocks. Currently the
only other block implemented is CMU_HSI0, which provides
clocks for the USB part of the SoC.
Also, device-tree binding definitions added for these blocks:
- CMU_TOP
- CMU_HSI0
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-1-57f07080f9e4@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Document the device tree bindings for the Renesas RZ/G3E SoC
Clock Pulse Generator (CPG).
Also define constants for the core clocks of the RZ/G3E SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add clock IDs for the slow clock controller. Previously, raw numbers
were used (0 or 1) for clocks generated by the slow clock controller. This
leads to confusion and wrong IDs were used on few device trees. To avoid
this add macros.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240826173116.3628337-2-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Add device tree bindings for global clock controller on QCS615 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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