summaryrefslogtreecommitdiff
path: root/include/dt-bindings/clock/gxbb-clkc.h
AgeCommit message (Collapse)Author
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clkidsJerome Brunet
Add the clkids for the clocks feeding the input0 of the mmc controllers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson-gxbb: expose almost every clock in the bindingsJerome Brunet
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-29clk: meson-gxbb: un-export the CPU clockMartin Blumenstingl
The CPU clock defined in the Meson GX clock driver is actually a left-over from the Meson8b clock controller. Un-export the clock so we can remove it from the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose UART clocksHelmut Klein
Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy the commit message to match similar change] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose SPICC gateNeil Armstrong
Expose the SPICC gate clock to enable the SPICC controller. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy commit message to match similar changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose spdif master clockJerome Brunet
Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose i2s master clockJerome Brunet
Expose cts_amclk in the device tree bindings Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose spdif clock gatesJerome Brunet
Expose the clock gates required for the spdif output Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-09Merge tag 'armsoc-dt64' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Olof Johansson: "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller changes, but also some new platforms that are worth mentioning: - Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook Plus (Kevin) - Orange Pi PC2 (Allwinner H5) - Freescale LS2088A and LS1088A SoCs - Expanded support for Nvidia Tegra186 (and Jetson TX2)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits) arm64: dts: Add basic DT to support Spreadtrum's SP9860G arm64: dts: exynos: Use - instead of @ for DT OPP entries arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board arm64: dts: juno: add information about L1 and L2 caches arm64: dts: juno: fix few unit address format warnings arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board ...
2017-04-04clk: meson-gxbb: Expose GP0 dt-bindings clock idNeil Armstrong
This patch exposes the GP0 PLL clock id in the dt bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-5-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Add MALI clock IDSNeil Armstrong
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-2-git-send-email-narmstrong@baylibre.com
2017-04-04dt-bindings: clk: gxbb: expose i2s output clock gatesJerome Brunet
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-16clk: meson-gxbb: expose clock CLKID_RNG0Heiner Kallweit
Expose clock CLKID_RNG0 which is needed for the HW random number generator. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-23clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18clk: meson-gxbb: Export HDMI clocksNeil Armstrong
Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose i2c clocksJerome Brunet
I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose USB clocksMartin Blumenstingl
USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose spifc clockJerome Brunet
SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose MPLL2 clock for use by DTMartin Blumenstingl
This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-02clk: meson-gxbb: Export PWM related clocks for DTNeil Armstrong
Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com
2016-08-15clk: gxbb: add MMC gate clocks, and expose for DTKevin Hilman
Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-15Revert "clk: gxbb: expose CLKID_MMC_PCLK"Michael Turquette
This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-07-07clk: gxbb: expose CLKID_MMC_PCLKKevin Hilman
The MMC_PCLK is needed for the SD/eMMC driver, expose to DT (and comment out in clk driver) Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160707033837.20029-1-khilman@baylibre.com
2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 06:01:50 +0000