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2020-07-08phy: allwinner: phy-sun6i-mipi-dphy: Constify structsRikard Falkeborn
sun6i_dphy_ops and sun6i_dphy_regmap_config are not modified so make them const structs to allow the compiler to put them in read-only memory. Before: text data bss dec hex filename 4407 1944 64 6415 190f drivers/phy/allwinner/phy-sun6i-mipi-dphy.o After: text data bss dec hex filename 4835 1496 64 6395 18fb drivers/phy/allwinner/phy-sun6i-mipi-dphy.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20200629195727.9717-1-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-08phy: ti-pipe3: remove set but unused variableVinod Koul
ti_pipe3_power_on() sets variable 'ret' but never uses it, so remove it. drivers/phy/ti/phy-ti-pipe3.c:340:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] Link: https://lore.kernel.org/r/20200629145010.122675-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-08phy: ti: dm816x: remove set but unused variableVinod Koul
dm816x_usb_phy_init() sets variable 'error' but never uses it, so remove it. drivers/phy/ti/phy-dm816x-usb.c:85:6: warning: variable ‘error’ set but not used [-Wunused-but-set-variable] Link: https://lore.kernel.org/r/20200629145010.122675-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-08phy: core: Document function argsVinod Koul
Some function arguments are missing from documentation prompting validation kernel doc script to complain: drivers/phy/phy-core.c:1078: warning: Function parameter or member 'children' not described in '__devm_of_phy_provider_register' drivers/phy/phy-core.c:1125: warning: Function parameter or member 'phy_provider' not described in 'devm_of_phy_provider_unregister' Add the documentation for these Link: https://lore.kernel.org/r/20200629145010.122675-2-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-08phy: core: fix code style in devm_of_phy_provider_unregisterVinod Koul
Documentation/process/coding-style.rst says: "functions: they have the opening brace at the beginning of the next line" devm_of_phy_provider_unregister() function has opening brace at same line, so fix it up. Link: https://lore.kernel.org/r/20200629145010.122675-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-08phy: qcom: remove ufs qmp phy driverVinod Koul
The UFS specific QMP PHY driver started off supporting the 14nm and 20nm hardware. With the 20nm support marked broken for a long time and the 14nm support added to the common QMP PHY, this driver has not been used in a while. So delete it Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200629145452.123035-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-01phy: zynqmp: Fix unused-function compiler warningTobias Klauser
Mark xpsgtr_suspend and xpsgtr_resume as __maybe_unused to fix the following compiler warning when building with !CONFIG_PM_SLEEP: drivers/phy/xilinx/phy-zynqmp.c:830:12: warning: ‘xpsgtr_resume’ defined but not used [-Wunused-function] 830 | static int xpsgtr_resume(struct device *dev) | ^~~~~~~~~~~~~ drivers/phy/xilinx/phy-zynqmp.c:819:12: warning: ‘xpsgtr_suspend’ defined but not used [-Wunused-function] 819 | static int xpsgtr_suspend(struct device *dev) | ^~~~~~~~~~~~~~ Also drop the existing #ifdef CONFIG_PM so the functions are always compile-checked regardless of CONFIG_PM and/or CONFIG_PM_SLEEP being set. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Link: https://lore.kernel.org/r/20200701141017.26931-1-tklauser@distanz.ch Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit TransceiverAnurag Kumar Vulisha
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-snps: Add a set mode callbackWesley Cheng
The set mode handler is used to keep track of the current role of the device. This is used for enabling certain resources within the PHY depending on if the device is behaving as a host or device. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/20200625195444.15130-3-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-snps: Add runtime suspend and resume handlersWesley Cheng
Allow for the PHY to be put into a powered down state when possible. Add the required suspend and resume callbacks, which will determine what resources can be turned off depending on the cable status. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/20200625195444.15130-2-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-qmp: Add QMP V4 USB3 PHY support for sm8250Jonathan Marek
Add both the DP and UNI PHY for primary/secondary usb controllers. The tables are very similar to sm8150 (serdes_tbl is identical), but there are some differences. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-4-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-qmp: Add QMP V4 USB3 UNIPHYJonathan Marek
Add support for the USB3 PHY used by the secondary usb controller on sm8150 Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-3-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-qmp: Allow different values for second laneJonathan Marek
The primary USB PHY on sm8250 sets some values differently for the second lane. This makes it possible to represent that. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-2-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-25phy: sun4i-usb: fix dereference of pointer phy0 before it is null checkedColin Ian King
Currently pointer phy0 is being dereferenced via the assignment of phy on the call to phy_get_drvdata before phy0 is null checked, this can lead to a null pointer dereference. Fix this by performing the null check on phy0 before the call to phy_get_drvdata. Also replace the phy0 == NULL check with the more usual !phy0 idiom. Addresses-Coverity: ("Dereference before null check") Fixes: e6f32efb1b12 ("phy: sun4i-usb: Make sure to disable PHY0 passby for peripheral mode") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200625124428.83564-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: qcom-qusb2: Add ipq8074 device compatibleSivaprakash Murugesan
Add ipq8074 qusb2 device compatible for high speed usb support. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Tested-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Link: https://lore.kernel.org/r/1591625479-4483-5-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: qcom-qmp: Add USB QMP PHY support for IPQ8074Sivaprakash Murugesan
Add QMP USB PHY found in IPQ8074 Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Tested-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: exynos: Rename Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200617152803.17941-1-krzk@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: Remove CONFIG_ARCH_* check for related subdir in MakefileTiezhu Yang
If CONFIG_ARCH_ROCKCHIP is not set but COMPILE_TEST is set, the file in the subdir rockchip can not be built due to CONFIG_ARCH_ROCKCHIP check in drivers/phy/Makefile. Since the related configs in drivers/phy/rockchip/Kconfig depend on ARCH_ROCKCHIP, so remove CONFIG_ARCH_ROCKCHIP check for subdir rockchip in drivers/phy/Makefile. The other CONFIG_ARCH_* about allwinner, amlogic, mediatek, renesas and tegra have the same situation, so remove them too. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/1590412138-13903-2-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: rockchip: Fix return value of inno_dsidphy_probe()Tiezhu Yang
When call function devm_platform_ioremap_resource(), we should use IS_ERR() to check the return value and return PTR_ERR() if failed. Fixes: b7535a3bc0ba ("phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/1590412138-13903-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: ti: j721e-wiz: Constify structsRikard Falkeborn
clk_div_table and wiz_regmap_config are not modified and can therefore be made const to allow the compiler to put them in read-only memory. Before: text data bss dec hex filename 20265 7044 64 27373 6aed drivers/phy/ti/phy-j721e-wiz.o After: text data bss dec hex filename 20649 6660 64 27373 6aed drivers/phy/ti/phy-j721e-wiz.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200524095516.25227-3-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: ti: am654-serdes: Constify regmap_configRikard Falkeborn
regmap_config is not modified and can be made static to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 12328 3644 64 16036 3ea4 drivers/phy/ti/phy-am654-serdes.o After: text data bss dec hex filename 12648 3324 64 16036 3ea4 drivers/phy/ti/phy-am654-serdes.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200524095516.25227-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: intel: fix enum type mismatch warningArnd Bergmann
clang points out that a local variable is initialized with an enum value of the wrong type: drivers/phy/intel/phy-intel-combo.c:202:34: error: implicit conversion from enumeration type 'enum intel_phy_mode' to different enumeration type 'enum intel_combo_mode' [-Werror,-Wenum-conversion] enum intel_combo_mode cb_mode = PHY_PCIE_MODE; ~~~~~~~ ^~~~~~~~~~~~~ >From reading the code, it seems that this was not only the wrong type, but not even supposed to be a code path that can happen in practice. Change the code to have no default phy mode but instead return an error for invalid input. Fixes: ac0a95a3ea78 ("phy: intel: Add driver support for ComboPhy") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Dilip Kota <eswara.kota@linux.intel.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20200527134518.908624-1-arnd@arndb.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: intel: Fix compilation error on FIELD_PREP usageDilip Kota
FIELD_PREP expects constant arguments. Istead of doing FIELD_PREP operation on the arguments of combo_phy_w32_off_mask(), pass the final FIELD_PREP value as an argument. Error reported as: In file included from include/linux/build_bug.h:5, from include/linux/bitfield.h:10, from drivers/phy/intel/phy-intel-combo.c:8: drivers/phy/intel/phy-intel-combo.c: In function 'combo_phy_w32_off_mask': include/linux/bitfield.h:52:28: warning: comparison is always false due to limited range of data type [-Wtype-limits] include/linux/compiler.h:350:38: error: call to '__compiletime_assert_37' declared with attribute error: FIELD_PREP: mask is not constant 94 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); | ^~~~~~~~~~~~~~~~ drivers/phy/intel/phy-intel-combo.c:137:13: note: in expansion of macro 'FIELD_PREP' 137 | reg_val |= FIELD_PREP(mask, val); | ^~~~~~~~~~ ../include/linux/compiler.h:392:38: error: call to__compiletime_assert_137 declared with attribute error: BUILD_BUG_ON failed: (((mask) + (1ULL << (__builtin_ffsll(mask) - 1))) & (((mask) + (1ULL << (__builtin_ffsll(mask) - 1))) - 1)) != 0 _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ../include/linux/bitfield.h:94:3: note: in expansion of macro __BF_FIELD_CHECK __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~~~~~~~~~~~~~ ../drivers/phy/intel/phy-intel-combo.c:137:13: note: in expansion of macro FIELD_PREP reg_val |= FIELD_PREP(mask, val); ^~~~~~~~~~ Fixes: ac0a95a3ea78 ("phy: intel: Add driver support for ComboPhy") Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Link: https://lore.kernel.org/r/8a309dd3c238efbaa59d1649704255d6f8b6c9c5.1590575358.git.eswara.kota@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-15phy: samsung: Replace zero-length array with flexible-arrayGustavo A. R. Silva
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://github.com/KSPP/linux/issues/21 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
2020-05-25Merge tag 'usb-for-v5.8' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: USB: changes for v5.8 merge window Rather busy cycle. We have a total 99 non-merge commits going into v5.8 merge window. The majority of the changes are in dwc3 this around (31.7% of all changes). It's composed mostly Thinh's recent updates to get dwc3 to behave correctly with stream transfers. We have also have Roger's for Keystone platforms and Neil's updates for the meson glue layer. Apart from those, we have the usual set of non-critical fixes, new device IDs, spelling fixes all over the place. Signed-off-by: Felipe Balbi <balbi@kernel.org> * tag 'usb-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: (99 commits) usb: dwc3: keystone: Turn on USB3 PHY before controller dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property dt-bindings: usb: convert keystone-usb.txt to YAML usb: dwc3: gadget: Check for prepared TRBs usb: gadget: Fix issue with config_ep_by_speed function usb: cdns3: ep0: delete the redundant status stage usb: dwc2: Update Core Reset programming flow. usb: gadget: fsl: Fix a wrong judgment in fsl_udc_probe() usb: gadget: fix potential double-free in m66592_probe. usb: cdns3: Fix runtime PM imbalance on error usb: gadget: lpc32xx_udc: don't dereference ep pointer before null check usb: dwc3: Increase timeout for CmdAct cleared by device controller USB: dummy-hcd: use configurable endpoint naming scheme usb: cdns3: gadget: assign interrupt number to USB gadget structure usb: gadget: core: sync interrupt before unbind the udc arm64: dts: qcom: sc7180: Add interconnect properties for USB arm64: dts: qcom: sdm845: Add interconnect properties for USB dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver ARM: dts: at91: Remove the USB EP child node dt-bindings: usb: atmel: Mark EP child node as deprecated ...
2020-05-25phy: amlogic: meson-gxl-usb3: remove code for non-existing PHYMartin Blumenstingl
The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-g12a-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
2020-05-22Merge tag 'phy-for-5.8' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next Kishon writes: phy: for 5.8 *) Add new PHY driver to support Cadence SALVO PHY which supports USB3 & USB2 *) Add new PHY driver to support Intel ComboPhy which supports PCIe, SATA and EMAC *) Add new PHY driver for Qualcomm IPQ40xx USB PHY *) Add new PHY driver for Synopsys FemtoPHY V2 driver used in Qualcomm SOCs *) Add support for Qualcomm SM8250 UFS PHY and SM8150 QMP USB3 PHY in qcom-qmp-phy driver *) Add support for Amlogic USB2 PHY on Meson8m2 in phy-meson8b-usb2 driver *) Add DisplayPort mode support in Wiz (TI Cadence PHY wrapper), to enable eDP in TI's J721E SoC *) Add support for super speed USB PHY in TI's AM654 SoC *) Add fix in Broadcom Stingray USB PHY to get USB PHY PLL lock reliably *) Add fix in Samsung phy-s5pv210-usb2 to get USB working on s5pv210 *) Add fix in Amlogic phy-meson8b-usb2 to get host only mode working on Meson8 *) Add fix in Cadence phy-cadence-sierra to get USB3 device disconnect issue *) Convert meson8b-usb2-phy, qcom-qmp-phy, rcar-gen3-phy-usb2 and rcar-gen3-phy-usb3 device tree binding to YAML schema *) Minor fixes and cleanups in phy-cpcap-usb, j721e-wiz, omap-usb2, phy-bcm-sr-usb, phy-brcm-usb PHY driver Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) phy: intel: Add driver support for ComboPhy dt-bindings: phy: Add YAML schemas for Intel ComboPhy dt-bindings: phy: Add PHY_TYPE_XPCS definition phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180 dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml phy: cadence: sierra: Fix for USB3 U1/U2 state phy: ti: am654: add support for USB super-speed phy: ti: am654: show up in regmap debugfs drivers: phy: sr-usb: do not use internal fsm for USB2 phy init dt-bindings: phy: renesas: usb3-phy: add r8a77961 support dt-bindings: phy: renesas: usb3-phy: convert bindings to json-schema dt-bindings: phy: renesas: usb2-phy: add r8a77961 support dt-bindings: phy: renesas: usb2-phy: convert bindings to json-schema phy: qcom-qmp: Ensure register indirection arrays initialized phy: omap-usb2: Clean up exported header phy: phy-bcm-ns2-usbdrd: Constify phy_ops phy: phy-brcm-usb: Constify static structs phy: sr-usb: Constify phy_ops ...
2020-05-19phy: intel: Add driver support for ComboPhyDilip Kota
ComboPhy subsystem provides PHYs for various controllers like PCIe, SATA and EMAC. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/7b313826f46b9006a3ba98c0613e8f88f293a074.1589868358.git.eswara.kota@linux.intel.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-19phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180Sandeep Maheswaram
Adding QMP v3 USB3 PHY support for SC7180. Adding only usb phy reset in the list to avoid reset of DP block. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1589510358-3865-5-git-send-email-sanm@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-18phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar
Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by: Sanket Parmar <sparmar@cadence.com> Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.com Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: ti: am654: add support for USB super-speedRoger Quadros
The SERDES PHY can support USB super-speed lane. Add support for that. Signed-off-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200513131254.10497-3-rogerq@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: ti: am654: show up in regmap debugfsRoger Quadros
The max_register property must be set in order to show up the registers in debugfs. Signed-off-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200513131254.10497-2-rogerq@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18drivers: phy: sr-usb: do not use internal fsm for USB2 phy initBharat Gooty
During different reboot cycles, USB PHY PLL may not always lock during initialization and therefore can cause USB to be not usable. Hence do not use internal FSM programming sequence for the USB PHY initialization. Fixes: 4dcddbb38b64 ("phy: sr-usb: Add Stingray USB PHY driver") Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Link: https://lore.kernel.org/r/20200513173947.10919-1-rayagonda.kokatanur@broadcom.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: qcom-qmp: Ensure register indirection arrays initializedBjorn Andersson
It's possible that struct qmp_phy_cfg->regs references an array that is smaller than the possible register lookups that is going to be performed, with the resulting out-of-bounds read resulting in undefined behavior. One such example is when during qcom_qmp_phy_com_init() performs a qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with msm8996_ufsphy_regs_layout only being 12 entries long. Solve this by inflating all "regs_layout" arrays to ensure that any remaining entries are zero-initialized, as expected by the code. Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: omap-usb2: Clean up exported headerRoger Quadros
Move private definitions from header to phy-omap-usb2.c file. Get rid of unused data structures usb_dpll_params and omap_usb_phy_type. Signed-off-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200515080518.26870-2-rogerq@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: phy-bcm-ns2-usbdrd: Constify phy_opsRikard Falkeborn
phy_ops are never modified and can therefore be made const to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 7831 3144 128 11103 2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o After: text data bss dec hex filename 7959 3016 128 11103 2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-2-rikard.falkeborn@gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: phy-brcm-usb: Constify static structsRikard Falkeborn
A number of structs were not modified and can therefore be made const to allow the compiler to put them in read-only memory. In order to do so, update a few functions that don't modify there input to take pointers to const. Before: text data bss dec hex filename 15511 6448 64 22023 5607 drivers/phy/broadcom/phy-brcm-usb.o After: text data bss dec hex filename 16058 5936 64 22058 562a drivers/phy/broadcom/phy-brcm-usb.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-4-rikard.falkeborn@gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: sr-usb: Constify phy_opsRikard Falkeborn
phy_ops are never modified and can therefore be made const to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 4310 1244 0 5554 15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o After: text data bss dec hex filename 4438 1116 0 5554 15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-3-rikard.falkeborn@gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-15phy: phy-cadence-salvo: add phy .init APIPeter Chen
The .init is used for one-time PHY's initialization, and .power_on is called many times during the device lifecycle. Signed-off-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200513125605.5545-1-peter.chen@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: Add a compatible string for Meson8m2Martin Blumenstingl
The 3.10 vendor kernel sets the ACA_ENABLE bit on Meson8b, Meson8m2 and GXBB, but not on Meson8. Add a compatible string for Meson8m2 which also sets that bit. While here, also update the Kconfig text and MODULE_DESCRIPTION. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-7-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-onMartin Blumenstingl
The vendor driver unsets the set_iddig bit during power-on as well and sets it when suspending the PHY. I did not notice this in the vendor driver first, because it's part of the dwc_otg driver there (instead of their PHY code). While here, also add all other REG_DBG_UART register bit definitions. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-6-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: Don't set REG_ADP_BC_ACA_ENABLE on Meson8Martin Blumenstingl
Skip setting REG_ADP_BC_ACA_ENABLE on Meson8 SoCs and polling for the REG_ADP_BC_ACA_PIN_FLOAT bit. The vendor also skips this part on Meson8 SoCs. This fixes initialization of the host-only USB PHY on Meson8 which would otherwise fail with "USB ID detect failed!". Fixes: 4a3449d1a0a10c ("phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs") Reported-by: Thomas Graichen <thomas.graichen@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-5-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: Use a MMIO regmapMartin Blumenstingl
Using a MMIO regmap and switch to regmap_update_bits() to simplify the code in the driver. Also switch to devm_platform_ioremap_resource() instead of open-coding it. No functional changes intended. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-4-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-13phy: intel-lgm-emmc: Add architecture dependencyGeert Uytterhoeven
The Intel eMMC PHY is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PHY_INTEL_EMMC config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507113626.24026-3-geert+renesas@glider.be Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13phy: ti: j721e-wiz: Fix some error return code in wiz_probe()Wei Yongjun
Fix to return negative error code from some error handling cases instead of 0, as done elsewhere in this function. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200507054109.110849-1-weiyongjun1@huawei.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13phy: cpcap-usb: Remove some useless codeChristophe JAILLET
Axe a clk that is unused in the driver. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20200507203127.202197-1-christophe.jaillet@wanadoo.fr Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13phy: samsung: s5pv210-usb2: Add delay after resetJonathan Bakker
The USB phy takes some time to reset, so make sure we give it to it. The delay length was taken from the 4x12 phy driver. This manifested in issues with the DWC2 driver since commit fe369e1826b3 ("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.") where the endianness check would read the DWC ID as 0 due to the phy still resetting, resulting in the wrong endian mode being chosen. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-07phy: cadence: salvo: add salvo phy driverPeter Chen
Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2. According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are later evolutions from it, and their sequence overlap is minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY drivers. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-05phy: qcom-qmp: Rename UFS PCS QMP v4 registersWesley Cheng
The UFS QMP v4 PHY has a largely different register set versus USB and PCIe. Rename the register offsets to denote that the value is specific for the UFS PCS register. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USBWesley Cheng
The register map for SM8150 QMP USB SSPHY has moved QPHY_POWER_DOWN_CONTROL to a different offset. Allow for an offset in the register table to override default value if it is a DP capable PHY. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-03 02:32:17 +0000