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2025-02-04phy: rockchip: naneng-combphy: compatible reset with old DTChukun Pan
The device tree of RK3568 did not specify reset-names before. So add fallback to old behaviour to be compatible with old DT. Fixes: fbcbffbac994 ("phy: rockchip: naneng-combphy: fix phy reset") Cc: Jianfeng Liu <liujianfeng1994@gmail.com> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250106100001.1344418-2-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-04phy: rockchip: fix Kconfig dependency moreArnd Bergmann
A previous patch ensured that USB Type C connector support is enabled, but it is still possible to build the phy driver without enabling CONFIG_USB (host support) or CONFIG_USB_GADGET (device support), and in that case the common helper functions are unavailable: aarch64-linux-ld: drivers/phy/rockchip/phy-rockchip-usbdp.o: in function `rk_udphy_probe': phy-rockchip-usbdp.c:(.text+0xe74): undefined reference to `usb_get_maximum_speed' Select CONFIG_USB_COMMON directly here, like we do in some other phy drivers, to make sure this is available even when actual USB support is disabled or in a loadable module that cannot be reached from a built-in phy driver. Fixes: 9c79b779643e ("phy: rockchip: fix CONFIG_TYPEC dependency") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250122065249.1390081-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-01-29Merge tag 'phy-for-6.14' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Lots of Qualcomm and Rockchip device support. New Support: - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY - Rockchip rk3576 combo phy support Updates: - Drop Shengyang for JH7110 maintainer - Freescale hdmi register calculation optimization - Rockchip pcie phy mutex and regmap updates" * tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits) dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY phy: rockchip: phy-rockchip-typec: Fix Copyright description dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs phy: qcom-qusb2: Add support for QCS615 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings phy: core: Simplify API of_phy_simple_xlate() implementation phy: sun4i-usb: Remove unused of_gpio.h phy: HiSilicon: Don't use "proxy" headers phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle() phy: qualcomm: qmp-pcie: add support for SAR2130P phy: qualcomm: qmp-pcie: define several new registers phy: qualcomm: qmp-pcie: split PCS_LANE1 region phy: qualcomm: qmp-combo: add support for SAR2130P dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found phy: freescale: fsl-samsung-hdmi: Expand Integer divider range phy: rockchip-naneng-combo: add rk3576 support dt-bindings: phy: rockchip: add rk3576 compatible ...
2024-12-25phy: rockchip: phy-rockchip-typec: Fix Copyright descriptionAndy Yan
The company name has update to Rockchip Electronics Co., Ltd. since 2021. And change Co.Ltd to Co., Ltd. to fix mail server warning: DBL_SPAM(6.50)[co.ltd:url]; Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241216100739.3726293-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: rockchip: samsung-hdptx: Set drvdata before enabling runtime PMCristian Ciocaltea
In some cases, rk_hdptx_phy_runtime_resume() may be invoked before platform_set_drvdata() is executed in ->probe(), leading to a NULL pointer dereference when using the return of dev_get_drvdata(). Ensure platform_set_drvdata() is called before devm_pm_runtime_enable(). Reported-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241023-phy-sam-hdptx-rpm-fix-v1-1-87f4c994e346@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: rockchip-naneng-combo: add rk3576 supportKever Yang
Rockchip RK3576 integrates two naneng-combo PHY, PHY0 is used for PCIE and SATA, PHY1 is used for PCIE, SATA and USB3. This adds device specific data support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Test-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20241106021357.19782-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip: naneng-combphy: fix phy resetChukun Pan
Currently, the USB port via combophy on the RK3528/RK3588 SoC is broken. usb usb8-port1: Cannot enable. Maybe the USB cable is bad? This is due to the combphy of RK3528/RK3588 SoC has multiple resets, but only "phy resets" need assert and deassert, "apb resets" don't need. So change the driver to only match the phy resets, which is also what the vendor kernel does. Fixes: 7160820d742a ("phy: rockchip: add naneng combo phy for RK3568") Cc: FUKAUMI Naoki <naoki@radxa.com> Cc: Michael Zimmermann <sigmaepsilon92@gmail.com> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241122073006.99309-2-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip-pcie: Use guard notation when acquiring mutexAnand Moon
Using guard notation makes the code more compact and error handling more robust by ensuring that mutexes are released in all code paths when control leaves critical section. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20241012071919.3726-7-linux.amoon@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip-pcie: Refactor mutex handling in rockchip_pcie_phy_power_on()Anand Moon
Refactor the mutex handling in the rockchip_pcie_phy_power_on() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_deassert() or regmap_read_poll_timeout() function, with 0 indicating success and an error code indicating failure. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20241012071919.3726-6-linux.amoon@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip-pcie: Refactor mutex handling in rockchip_pcie_phy_power_off()Anand Moon
Refactor the mutex handling in the rockchip_pcie_phy_power_off() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_assert() function, with 0 indicating success and an error code indicating failure Signed-off-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20241012071919.3726-5-linux.amoon@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip-pcie: Use regmap_read_poll_timeout() for PCIe reference clk ↵Anand Moon
PLL status Replace open-coded phy PCIe reference clk PLL status polling with regmap_read_poll_timeout API. This change simplifies the code without altering functionality. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20241012071919.3726-4-linux.amoon@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip-pcie: Use devm_clk_get_enabled() helperAnand Moon
Use devm_clk_get_enabled() instead of devm_clk_get() to make the code cleaner and avoid calling clk_disable_unprepare(), as this is exactly what this function does. Use the dev_err_probe() helper to simplify error handling during probe. Refactor the mutex handling in the rockchip_pcie_phy_init() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_assert() function, with 0 indicating success and an error code indicating failure Signed-off-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20241012071919.3726-3-linux.amoon@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip-pcie: Simplify error handling with dev_err_probe()Anand Moon
Use the dev_err_probe() helper to simplify error handling during probe. This also handle scenario, when -EDEFER is returned and useless error is printed. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20241012071919.3726-2-linux.amoon@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-11-27Merge tag 'phy-for-6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - ST STM32MP25 combophy support - Sparx5 support for lan969x serdes and updates to driver to support this - NXP PTN3222 eUSB2 to USB2 redriver - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2 support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP UFS PHY support and SA8775P eDP PHY support - Rockchip rk3576 usbdp and rk3576 usb2 phy support - Binding for Microchip ATA6561 can phy Updates: - Freescale driver updates from hdmi support - Conversion of rockchip rk3228 hdmi phy binding to yaml - Broadcom usb2-phy deprecated support dropped and USB init array update for BCM4908 - TI USXGMII mode support in J7200 - Switch back to platform_driver::remove() subsystem update" * tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits) phy: qcom: qmp: Fix lecacy-legacy typo phy: lan969x-serdes: add support for lan969x serdes driver dt-bindings: phy: sparx5: document lan969x phy: sparx5-serdes: add support for branching on chip type phy: sparx5-serdes: add indirection layer to register macros phy: sparx5-serdes: add function for getting the CMU index phy: sparx5-serdes: add ops to match data phy: sparx5-serdes: add constant for the number of CMU's phy: sparx5-serdes: add constants to match data phy: sparx5-serdes: add support for private match data phy: bcm-ns-usb2: drop support for old binding variant dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll() phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l() phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out() phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL ...
2024-10-17phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLLAndy Yan
RST_PHY/RST_ROPLL/RST_LCPLL are used for debug only on rk3588, and they are not exported on rk3576, no need to request it in driver. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20240920093629.7410-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: phy-rockchip-samsung-hdptx: Depend on CONFIG_COMMON_CLKCristian Ciocaltea
Ensure CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX depends on CONFIG_COMMON_CLK to fix the following link errors when compile testing some random kernel configurations: m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.o: in function `rk_hdptx_phy_clk_register': drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1031:(.text+0x470): undefined reference to `__clk_get_name' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1036:(.text+0x4ba): undefined reference to `devm_clk_hw_register' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1040:(.text+0x4d2): undefined reference to `of_clk_hw_simple_get' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1040:(.text+0x4da): undefined reference to `devm_of_clk_add_hw_provider' Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409180305.53PXymZn-lkp@intel.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240923-sam-hdptx-link-fix-v1-1-8d10d7456305@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/phy/ to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. While touching these files, make indention of the struct initializer consistent in several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: usbdp: add rk3576 device match dataFrank Wang
This adds RK3576 device match data support. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: inno-usb2: Add usb2 phys support for rk3576William Wu
The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has one port. This adds device specific data for it. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: inno-usb2: convert clock management to bulkFrank Wang
Since some Rockchip SoCs (e.g RK3576) have more than one clock, this converts the clock management from single to bulk method to make the driver more flexible. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Use dev_err_probe() in the probe pathDragan Simic
Improve error handling in the probe path by using function dev_err_probe() instead of function dev_err(), where appropriate. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/d4ccd9fc278fb46ea868406bf77811ee507f0e4e.1725524803.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Handle failed extcon allocation betterDragan Simic
Return the actual error code upon failure to allocate extcon device, instead of hardcoding -ENOMEM. Use dev_err_probe() to also log appropriate messages, which is fine because the containing function is used in the probe path. Helped-by: Heiko Stubner <heiko@sntech.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/cc4995aa3e569be6bc23ca126b41fba82d50eeee.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Perform trivial code cleanupsDragan Simic
Perform a few trivial code cleanups, e.g. to obey the reverse Christmas tree rule, to avoid use of "{ ... }" code blocks where they aren't really needed, or to avoid line wrapping by using the 100-column width better. No intended functional changes are introduced by these code cleanups. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/adce7309f6fd9e1191c53bab552a8531d1a71216.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-05phy: phy-rockchip-samsung-hdptx: Add clock provider supportCristian Ciocaltea
The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC CRU. It provides more accurate clock rates required by VOP2 to improve existing support for display modes handling, which is known to be problematic when dealing with non-integer refresh rates, among others. It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-4-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-05phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core levelCristian Ciocaltea
When a new PHY is created via [devm_]phy_create(), the runtime PM for it is not enabled unless the parent device (which creates the PHY) has its own runtime PM already enabled. Move the call to devm_pm_runtime_enable() before devm_phy_create() to enable runtime PM at PHY core level. With this change the ->power_on() and ->power_off() callbacks do not require explicit runtime PM management anymore, since the PHY core handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and phy_power_off() are invoked. Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and pm_runtime_put() helpers. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-2-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-05phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.hCristian Ciocaltea
Driver makes use of helpers from pm_runtime.h, but relies on the header file being implicitly included. Explicitly pull the header in to avoid potential build failures in some configurations. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-1-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCONCristian Ciocaltea
Compile testing configurations without REGMAP support enabled results in a bunch of errors being reported: ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type 569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { | ^~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’ 570 | .reg_bits = 32, | ^~~~~~~~ Note that selecting REGMAP alone is not enough, because of the following liker error: phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk' Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON, which implicitly enables REGMAP_MMIO as well. The rationale is that the driver has been already relying on the syscon functionality. Moreover, without MFD_SYSCON enabled, the test coverage is reduced, since the linker might not detect any potential undefined references following syscon_regmap_lookup_by_phandle() invocation in rk_hdptx_phy_probe() body. That is because the function would unconditionally return -ENOTSUP, hence the compiler is free to optimize out any unreachable code. Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as required by MFD_SYSCON. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-21Merge tag 'phy-for-6.10' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
2024-04-17phy: rockchip: fix CONFIG_TYPEC dependencyArnd Bergmann
The newly added driver causes a warning about missing dependencies by selecting CONFIG_TYPEC unconditionally: WARNING: unmet direct dependencies detected for TYPEC Depends on [n]: USB_SUPPORT [=n] Selected by [y]: - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y] WARNING: unmet direct dependencies detected for USB_COMMON Depends on [n]: USB_SUPPORT [=n] Selected by [y]: - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y] Since that is a user-visible option, it should not really be selected in the first place. Replace the 'select' with a 'depends on' as we have for similar drivers. Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-17phy: rockchip: usbdp: fix uninitialized variableSebastian Reichel
The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if the PHY is not using USB3 mode. Since the DisplayPort part is handled separately and the PHY does not support USB2 (which is routed to another PHY on Rockchip RK3588), the right exit code for this case is 0. Thus let's initialize the variable accordingly. Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-13phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-modeNiklas Cassel
>From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add support for the device tree property rockchip,rx-common-refclk-mode, such that the PCIe PHY can be used in configurations where the Root Complex and Endpoint are not using a common reference clock. Signed-off-by: Niklas Cassel <cassel@kernel.org> Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-12phy: rockchip: add usbdp combo phy driverSebastian Reichel
This adds a new USBDP combo PHY with Samsung IP block driver. The driver get lane mux and mapping info in 2 ways, supporting DisplayPort alternate mode or parsing from DT. When parsing from DT, the property "rockchip,dp-lane-mux" provide the DP mux and mapping info. This is needed when the PHY is not used with TypeC Alt-Mode. For example if the USB3 interface of the PHY is connected to a USB Type A connector and the DP interface is connected to a DisplayPort connector. When do DP link training, need to set lane number, link rate, swing, and pre-emphasis via PHY configure interface. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Co-developed-by: Zhang Yubing <yubing.zhang@rock-chips.com> Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-12phy: phy-rockchip-samsung-hdptx: Select CONFIG_RATIONALCristian Ciocaltea
Ensure CONFIG_RATIONAL is selected in order to fix the following link error with some kernel configurations: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.o: in function `rk_hdptx_ropll_tmds_cmn_config': phy-rockchip-samsung-hdptx.c:(.text+0x950): undefined reference to `rational_best_approximation' Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404090540.2l1TEkDF-lkp@intel.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240408222926.32708-1-cristian.ciocaltea@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-12Merge branch 'fixes' into nextVinod Koul
This brings rockchip,pcie3-phy changes into next which incoming patches are dependent on
2024-04-06phy: rockchip: naneng-combphy: Fix mux on rk3588Sebastian Reichel
The pcie1l0_sel and pcie1l1_sel bits in PCIESEL_CON configure the mux for PCIe1L0 and PCIe1L1 to either the PIPE Combo PHYs or the PCIe3 PHY. Thus this configuration interfers with the data-lanes configuration done by the PCIe3 PHY. RK3588 has three Combo PHYs. The first one has a dedicated PCIe controller and is not affected by this. For the other two Combo PHYs, there is one mux for each of them. pcie1l0_sel selects if PCIe 1L0 is muxed to Combo PHY 1 when bit is set to 0 or to the PCIe3 PHY when bit is set to 1. pcie1l1_sel selects if PCIe 1L1 is muxed to Combo PHY 2 when bit is set to 0 or to the PCIe3 PHY when bit is set to 1. Currently the code always muxes 1L0 and 1L1 to the Combi PHYs once one of them is being used in PCIe mode. This is obviously wrong when at least one of the ports should be muxed to the PCIe3 PHY. Fix this by introducing Combo PHY identification and then only setting up the required bit. Fixes: a03c44277253 ("phy: rockchip: Add naneng combo phy support for RK3588") Reported-by: Michal Tomek <mtdev79b@gmail.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-3-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-06phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bitsSebastian Reichel
Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but does not clear them because of an incorrect write mask. This fixes up the issue by using a newly introduced constant for the write mask. While at it also introduces a proper GENMASK based constant for the PCIE30_PHY_MODE. Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-06phy: rockchip-snps-pcie3: fix bifurcation on rk3588Michal Tomek
So far all RK3588 boards use fully aggregated PCIe. CM3588 is one of the few boards using this feature and apparently it is broken. The PHY offers the following mapping options: port 0 lane 0 - always mapped to controller 0 (4L) port 0 lane 1 - to controller 0 or 2 (1L0) port 1 lane 0 - to controller 0 or 1 (2L) port 1 lane 1 - to controller 0, 1 or 3 (1L1) The data-lanes DT property maps these as follows: 0 = no controller (unsupported by the HW) 1 = 4L 2 = 2L 3 = 1L0 4 = 1L1 That allows the following configurations with first column being the mainline data-lane mapping, second column being the downstream name, third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register values and final column being the user visible lane setup: <1 1 1 1> = AGGREG = [4 0] = x4 (aggregation) <1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.) <1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0) <1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1) <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports) The driver currently does not program PHP_GRF_PCIESEL correctly, which is fixed by this patch. As a side-effect the new logic is much simpler than the old logic. Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") Signed-off-by: Michal Tomek <mtdev79b@gmail.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05phy: rockchip: Fix typo in function namesRick Wertenbroek
Several functions had "rochchip" instead of "rockchip" in their name. Replace "rochchip" by "rockchip". Signed-off-By: Rick Wertenbroek <rick.wertenbroek@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-23phy: constify of_phandle_args in xlateKrzysztof Kozlowski
The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-16phy: rockchip: Add Samsung HDMI/eDP Combo PHY driverCristian Ciocaltea
Add driver for the HDMI/eDP TX Combo PHY found on Rockchip RK3588 SoC. The PHY is based on a Samsung IP block and supports HDMI 2.1 TMDS, FRL and eDP links. The maximum data rate is 12Gbps (FRL), while the minimum is 250Mbps (TMDS). Only the TMDS link is currently supported. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240214-phy-hdptx-v4-2-e7974f46c1a7@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27phy: phy-rockchip-inno-usb2: Add RK3128 supportAlex Bee
Add registers to support the 2-port usb2 phy found in RK312x SoC familiy. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231119121340.109025-3-knaerzche@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27phy: rockchip-inno-usb2: Split ID interrupt phy registersAlex Bee
Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID detection interrupt registers. However the current implementation assumes that falling and rising edge interrupt are always enabled in registers spanning over subsequent bits. That is not the case for RK3128's version of the phy and this implementation can't be used as-is, since there are bits with different purpose in between. This splits up the register definitions for id_det_en, id_det_en and id_det_clr registers in rising and falling edge variants. It's required as preparation to support RK3128's Innosilicon usb2 phy as well in this driver and matches pretty much to what the vendor does, so I'm not expecting issues for other SoCs with that change. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231119121340.109025-2-knaerzche@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13phy: rockchip-inno-usb2: Drop unnecessary DT includesRob Herring
Neither of_address.h or of_platform.h are used in the driver, so drop them. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231009172923.2457844-17-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13phy: Use device_get_match_data()Rob Herring
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231009172923.2457844-15-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: rockchip: inno-dsidphy: Add rv1126 supportJagan Teki
Add support for Rockchip RV1126 DSI-DPHY. The existing 2.5GHz phy timing table added for RK3568 is working as it is for RV1126 as well. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20230731110012.2913742-5-jagan@edgeble.ai Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-17phy: Explicitly include correct DT includesRob Herring
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: add more supported pre-pll ratesAlex Bee
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: force set_rate on power_onHuicong Xu
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <xhc@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-6-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg writeJonas Karlman
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-5-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rateJonas Karlman
no_c is not used in any calculation, lets remove it. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-4-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 23:41:37 +0000