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The Qualcomm SGMII SerDes PHY is a QMP PHY. As such, it uses standard
registers for QSERDES COM/RX/TX regions. Use register defines from the
existing headers.
Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-7-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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None of the PHYs supported by the USBC driver need power down delay.
Drop corresponding flag and code.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-6-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Move bit definitions for the common headers to the common phy-qcom-qmp.h
header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Split the DP PHY register definitions to separate headers, removing them
from the global one.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-4-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Move common init tables code to the common header phy-qcom-qmp-common.h.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-3-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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All PHYs supported by qmp-usb-legacy driver don't have issues with the
PCS region. Replace qmp_usb_legacy_iomap() with devm_of_iomap().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-2-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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All PHYs supported by usb-legacy have two lanes. Drop support for
single-lane configuration.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad DYbcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-1-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Align PCIe0 PHY settings with SM8550 latest PCIe PHY Hardware Programming
Guide.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Link: https://lore.kernel.org/r/1703742157-69840-3-git-send-email-quic_qianyu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Align PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware Programming
Guide.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Link: https://lore.kernel.org/r/1703742157-69840-2-git-send-email-quic_qianyu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add the X1E80100 G3 and G4 configurations.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-3-223c0556908a@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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For consistency, add the QMP v6 registers layout even though
they are the same as v5. Also switch all QMP v6 PHYs to use this
new layout.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-2-223c0556908a@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
separate serdes init sequence for IPQ6018. Since already existing IPQ9574
serdes init sequence is identical, just reuse it and fix failing USB3 mode
in IPQ6018.
Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Commit 2be22aae6b18 ("phy: qcom-qmp-usb: populate offsets configuration")
introduced register offsets to the driver but for ipq8074/ipq6018 they do
not match what was in the old style device tree. Example from old
ipq6018.dtsi:
<0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc */
which would translate to:
{.., .pcs = 0x800, .pcs_misc = 0x600, .tx = 0x200, .rx = 0x400 }
but was translated to:
{.., .pcs = 0x600, .tx = 0x200, .rx = 0x400 }
So split usb_offsets and fix USB initialization for IPQ8074 and IPQ6018.
Tested only on IPQ6018
Fixes: 2be22aae6b18 ("phy: qcom-qmp-usb: populate offsets configuration")
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1706026160-17520-2-git-send-email-mantas@8devices.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Provide PHY configuration for the USB QMP PHY for the SDM630 / SDM660
platforms.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-2-2fbd683aea77@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The QMP USB PHYs on msm8998, qcm2290 and some other platforms don't have
the PCS_MISC_CLAMP_ENABLE register. Instead they need to toggle the
register in the TCSR space. Make the new phy-qcom-qmp-usbc driver
correctly handle the clamp register.
Fixes: a51969fafc82 ("phy: qcom-qmp: Add QMP V3 USB3 PHY support for msm8998")
Fixes: 8abe5e778b2c ("phy: qcom-qmp: Add QCM2290 USB3 PHY support")
Cc: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-3-a950c223f10f@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The USB-C PHYs on the msm8998, QCM2290 and SM6115 platforms use special
register to control which lanes of the Type-C port are used for the
SuperSpeed USB connection. Mimic the qmp-combo driver and handle this
register.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240113-pmi632-typec-v2-12-182d9aa0a5b3@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Now as all dual-lane PHYs have been migrated to a new driver, drop
support for dual lanes configuration. If the PHY uses two lanes for USB,
it is symthom that it should use either a combo USB+DP or a USB-C PHY
driver.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240113-pmi632-typec-v2-11-182d9aa0a5b3@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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In preparation to adding Type-C handling for MSM8998, QCM2290 and SM6115
platforms, create new QMP USB-C PHY driver by splitting mentioned
platforms to a separate file. In future it will also be extended with
support for the DisplayPort handling. It will also be reused later for
such platforms as SDM660, SM6125, SM6150.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240113-pmi632-typec-v2-10-182d9aa0a5b3@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers.
To add HS-G5 support for SM8550, split the two sets of PHY settings into
their dedicated overlay tables, only the common parts of the two sets of
PHY settings are left in the .tbls.
Consider we are going to add even higher gear support in future, to avoid
adding more tables with different names, rename the .tbls_hs_g4 and make it
an array, a size of 2 is enough as of now.
In this case, .tbls alone is not a complete set of PHY settings, so either
tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
.tbls to become a complete set of PHY settings.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Link: https://lore.kernel.org/r/1703557892-1822-1-git-send-email-quic_cang@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The SC7180 UFS PHY is identical to the one found on SM7150. Add a
compatible for it.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-5-f7d1212c8ebb@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New Support:
- Qualcomm SM8650 UFS, PCIe and USB/DP Combo PHY, eUSB2 PHY, SDX75
USB3, X1E80100 USB3 support
- Mediatek MT8195 support
- Rockchip RK3128 usb2 support
- TI SGMII mode for J784S4
Updates:
- Qualcomm v7 register offsets updates
- Mediatek tphy support for force phy mode switch"
* tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (34 commits)
phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4
phy: ti: gmii-sel: Enable SGMII mode for J784S4
phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support
dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding
phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible
dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible
phy: mediatek: tphy: add support force phy mode switch
dt-bindings: phy: mediatek: tphy: add a property for force-mode switch
phy: phy-can-transceiver: insert space after include
phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header
phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY
phy: qcom-qmp: qserdes-txrx: Add v7 register offsets
phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets
phy: qcom-qmp: qserdes-com: Add v7 register offsets
phy: qcom-qmp: pcs-usb: Add v7 register offsets
phy: qcom-qmp: pcs: Add v7 register offsets
phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
...
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The X1E80100 platform has two instances of the USB3 UNI phy attached
to the multi-port USB controller, add definition for these.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-usb3-uniphy-x1e80100-v3-2-273814c300f8@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The X1E80100 has three copies of an USB/DP compbo PHY, add support for this
to the Qualcomm QMP PHY driver.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231201-x1e80100-phy-combo-v1-2-6938ec41f3ac@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The registers, which are being touched in current SM8550 UFS PHY settings,
and the values being programmed are mainly the ones working for HS-G4 mode,
meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
However, even consider HS-G4 mode only, some of them are incorrect and some
are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.
Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/1701520577-31163-10-git-send-email-quic_cang@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
Add the new qserdes TX RX offsets in a dedicated header file.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-7-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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There is a variant of V6 offsets that are different, the QMP PHY N4,
and it is found on the X1E80100 platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-6-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The X1E80100 platform bumps the HW version of QMP phy to v7 for USB
and PCIE g3x2. Add the new qserdes com offsets in a dedicated
header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-5-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The X1E80100 platform bumps the HW version of QMP phy to v7 for USB.
Add the new PCS USB specific offsets in a dedicated header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-4-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The X1E80100 platform bumps the HW version of QMP phy to v7 for USB,
and PCIe. Add the new PCS offsets in a dedicated header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-3-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add some missing v6.20 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-2-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add some missing V6 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-1-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Switch to using the new DRM_AUX_BRIDGE helper to create the
transparent DRM bridge device instead of handcoding corresponding
functionality.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-3-dmitry.baryshkov@linaro.org
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Add support for USB3 QMP PHY found in SDX75 platform.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231117061501.537529-1-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add QMP USB3/DP Combo PHY support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-7-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add QMP PCIe PHY support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-6-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add QMP UFS PHY support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-5-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add support for dual lane end point mode PHY found on sa8755p platform.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1697715430-30820-4-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The commit 39bbf82d8c2b ("phy: qcom-qmp: pcs-usb: Add v6 register
offsets") incorrectly added plain PCS registers to the PCS_USB header.
Move them to a proper location.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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For all other generations, we have been using just the QPHY prefix for
the PCS registers. Remove the _USB part of the QPHY_USB prefix.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Merge fixes into next as qmp phy patches on list depend on it
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There are devices in the wild, like the Sony Xperia 1 V that *require*
different tuning than the base design for USB to work.
Add support for overriding the necessary tuning values.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-4-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The vendor kernel zeroes out all tuning data outside the init sequence
as part of initialization. Follow suit to avoid UB.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-3-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Switch to regmap_fields, so that the values written into registers are
sanitized by their explicit sizes and the different registers are
structured in an iterable object to make external changes to the init
sequence simpler.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-2-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add phy init sequence and compatible string for IPQ5018
chipset.
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Link: https://lore.kernel.org/r/20230904063635.24975-3-quic_nsekar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Fix typo in the description of the 'succesfully'.
Signed-off-by: Bo Liu <liubo03@inspur.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230912114646.8452-1-liubo03@inspur.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Currently, PCS_USB registers that have their initialization data in a
pcs_usb_tbl table are never initialized. Fix that.
Fixes: fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region")
Reported-by: Adrien Thierry <athierry@redhat.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-2-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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There are two instances of the POWER_STATE_CONFIG1 register: one in
the PCS space and another one in PCS_USB.
The downstream init sequence pokes the latter one while we've been poking
the former one (and misnamed it as the latter one, impostor!). Fix that
up to avoid UB.
Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550")
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-1-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Fix the following Smatch complaint:
drivers/phy/qualcomm/phy-qcom-m31.c:175 m31usb_phy_init()
warn: variable dereferenced before check 'qphy->vreg' (see line 167)
drivers/phy/qualcomm/phy-qcom-m31.c
166
167 ret = regulator_enable(qphy->vreg);
^^^^^^^^^^
Unchecked dereference
168 if (ret) {
169 dev_err(&phy->dev, "failed to enable regulator, %d\n", ret);
170 return ret;
171 }
172
173 ret = clk_prepare_enable(qphy->clk);
174 if (ret) {
175 if (qphy->vreg)
^^^^^^^^^^
Checked too late
176 regulator_disable(qphy->vreg);
177 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
Since the phy will not get registered if qphy->vreg is NULL,
this check is not needed.
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/linux-phy/cbd26132-c624-44b7-a073-73222b287338@moroto.mountain/T/#u
Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver")
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/1694069452-3794-1-git-send-email-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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m31_ipq5332_regs is only used in phy-qcom-m31.c now, change
it to static.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20230824092356.1154839-1-yangyingliang@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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