| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-03-31 | phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY | Rohit Agarwal | |
| The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
| 2022-07-07 | phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers | Dmitry Baryshkov | |
| Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-19-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
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