| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-01-30 | phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 | Qiang Yu | |
| Align PCIe0 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Link: https://lore.kernel.org/r/1703742157-69840-3-git-send-email-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
| 2023-02-10 | phy: qcom-qmp: pcs-pcie: Add v6 register offsets | Abel Vesa | |
| The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
 |
index : linux/linux-stable.git | |
| Linux kernel stable tree | kernel.org maintainers |
| summaryrefslogtreecommitdiff |