| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-03-20 | phy: qcom-qmp-pcie: Add RC init sequence for SDX55 | Manivannan Sadhasivam | |
| Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
| 2022-07-07 | phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers | Dmitry Baryshkov | |
| Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
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