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path: root/drivers/phy/mediatek/phy-mtk-tphy.c
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2023-05-19phy: mediatek: tphy: add debugfs filesChunfeng Yun
These debugfs files are mainly used to make eye diagram test easier, especially helpful to do HQA test for a new IC without efuse enabled. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-24phy: mediatek: tphy: remove macros to prepare bitfield valueChunfeng Yun
Prefer to make use of FIELD_PREP() macro to prepare bitfield value, then no need local ones anymore. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220920090038.15133-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-20phy: phy-mtk-tphy: fix the phy type setting issueChunfeng Yun
The PHY type is not set if the index is non zero, prepare type value according to the index, like as mask value. Fixes: 39099a443358 ("phy: phy-mtk-tphy: support type switch by pericfg") Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220914060746.10004-7-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-20phy: phy-mtk-tphy: set utmi 0 register in init() opsChunfeng Yun
No need repeat to clear utmi 0 register in ->power_on() and ->power_off(), just do it in ->init() Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220914060746.10004-6-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-20phy: phy-mtk-tphy: disable gpio mode for all usb2 physChunfeng Yun
Disable DP/DM's GPIO mode for all usb2 phy, not only for the first usb2 phy which usually supports dual-role mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220914060746.10004-5-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-20phy: phy-mtk-tphy: disable hardware efuse when set INTRChunfeng Yun
INTR's value is able autoload from hardware efuse by default, when software tries to update its value, should disable hardware efuse firstly. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220914060746.10004-4-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-20phy: phy-mtk-tphy: add property to set pre-emphasisChunfeng Yun
Add a property to set usb2 phy's pre-emphasis, it's disabled by default on some SoCs. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220914060746.10004-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: phy-mtk-tphy: Fix duplicated argument in phy-mtk-tphyWan Jiabing
Fix following coccicheck warning: ./drivers/phy/mediatek/phy-mtk-tphy.c:994:6-29: duplicated argument to && or || The efuse_rx_imp is duplicate. Here should be efuse_tx_imp. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220107025050.787720-1-wanjiabing@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: phy-mtk-tphy: use new io helpers to access registerChunfeng Yun
Use new helpers mtk_phy_clear/set/update_bits() to access registers Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-5-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: phy-mtk-tphy: add support efuse settingChunfeng Yun
Due to some SoCs have a bit shift issue that will drop a bit for usb3 phy or pcie phy, fix it by adding software efuse reading and setting, but only support it optionally for version 2/3. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17phy: phy-mtk-tphy: remove error log of ioremap failureChunfeng Yun
devm_ioremap_resource() will print log if error happens. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629191987-20774-5-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17phy: phy-mtk-tphy: print error log using child deviceChunfeng Yun
Print error log using child devices instead of parent device. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629191987-20774-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17phy: phy-mtk-tphy: support type switch by pericfgChunfeng Yun
Add support type switch between USB3, PCIe, SATA and SGMII by pericfg register, this is used to take the place of efuse or jumper. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629191987-20774-3-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17phy: phy-mtk-tphy: use clock bulk to get clocksChunfeng Yun
Use clock bulk helpers to get/enable/disable clocks Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629191987-20774-2-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-06phy: phy-mtk-tphy: add support mt8195Chunfeng Yun
The controller is designed to use use PLL integer mode, but in fact used fractional mode for some ones on mt8195, this causes signal degradation (e.g. eye diagram test fail), fix it by switching PLL to 26Mhz from default 48Mhz to improve signal quality. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1627028562-23584-3-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-06phy: phy-mtk-tphy: support new hardware versionChunfeng Yun
The PHYA arch is updated, and doesn't support slew rate calibrate anymore on 7nm or advanced process, add a new version number to support it. Note: the FreqMeter bank is not used but reserved. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1627028562-23584-2-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-31phy: phy-mtk-tphy: Fix some resource leaks in mtk_phy_init()Tiezhu Yang
Use clk_disable_unprepare() in the error path of mtk_phy_init() to fix some resource leaks. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1621420659-15858-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-03-20phy: phy-mtk-tphy: add a new reference clockChunfeng Yun
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it, this can avoid confusion when support new platforms Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: make the ref clock optionalChunfeng Yun
Sometimes the reference clock of USB3 PHY comes from oscillator directly, and no need refer to a fixed-clock in DTS anymore if make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a property for internal resistanceChunfeng Yun
This is used to tune J-K voltage by internal R (resistance), the range is [0, 31], the resistance value is about 6.9K ohm for 0, 3.8K ohm for 31, and the step is 1K ohm Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a property for disconnect thresholdChunfeng Yun
This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional()Chunfeng Yun
Use devm_clk_get_optional() to get optional clock Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: core: rework phy_set_mode to accept phy mode and submodeGrygorii Strashko
Currently the attempt to add support for Ethernet interface mode PHY (MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and duplicate there values from phy_interface_t enum (or introduce more PHY callbacks) [1]. Both approaches are ineffective and would lead to fast bloating of enum phy_mode or struct phy_ops in the process of adding more PHYs for different subsystems which will make them unmaintainable. As discussed in [1] the solution could be to introduce dual level PHYs mode configuration - PHY mode and PHY submode. The PHY mode will define generic PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem specific interface mode. The last is usually already defined in corresponding subsystem headers (phy_interface_t for Ethernet, enum usb_device_speed for USB). This patch is cumulative change which refactors PHY framework code to support dual level PHYs mode configuration - PHY mode and PHY submode. It extends .set_mode() callback to support additional parameter "int submode" and converts all corresponding PHY drivers to support new .set_mode() callback declaration. The new extended PHY API int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) is introduced to support dual level PHYs mode configuration and existing phy_set_mode() API is converted to macros, so PHY framework consumers do not need to be changed (~21 matches). [1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-07-10phy: phy-mtk-tphy: add property for BC12Chunfeng Yun
Some platforms support BC12 which is disabled by default, here add a property to enable it if need Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-07-10phy: phy-mtk-tphy: add properties for eye diagram testChunfeng Yun
Add properties for Eye diagram test of HQA which sometimes need adjust some parameters of u2phy Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-07-10phy: phy-mtk-tphy: use SPDX license tagChunfeng Yun
Use SPDX-License-Identifier tag instead of the GPL license text Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-16phy: phy-mtk-tphy: add configurable parameters for slew rate calibrateChunfeng Yun
There are two parameters, ref_clk and coefficient, for U2 slew rate calibrate which may vary on different SoCs, here allow them to be configurable Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-16phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_enChunfeng Yun
The default value of mcu_bus_ck_gate_en is 1, if clear it, will prevent system to enter deep idle mode, so keep its default value and without affecting PCIe function. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-12-29phy: phy-mtk-tphy: use of_device_get_match_data()Chunfeng Yun
reduce the boilerplate code to get the specific data Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-12-29phy: phy-mtk-tphy: make shared banks optional for V1 TPHYChunfeng Yun
V1 TPHY for SATA doesn't have shared banks if it isn't shared with PCIe or USB, so make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-12-29phy: phy-mtk-tphy: use auto instead of force to bypass utmi signalsChunfeng Yun
When system is running, if usb2 phy is forced to bypass utmi signals, all PLL will be turned off, and it can't detect device connection anymore, so replace force mode with auto mode which can bypass utmi signals automatically if no device attached for normal flow. But keep the force mode to fix RX sensitivity degradation issue. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-10-23phy: phy-mtk-tphy: add set_mode callbackChunfeng Yun
This is used to force PHY with USB OTG function to enter a specific mode, and override OTG IDPIN(or IDDIG) signal. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-09-26phy: phy-mtk-tphy: fix NULL point of chip bankChunfeng Yun
Chip bank of version-1 is initialized as NULL, but it's used by pcie_phy_instance_power_on/off(), so assign it a right address. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-20phy: phy-mt65xx-usb3: add mediatek directory and rename fileChunfeng Yun
The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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