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path: root/drivers/pci/host
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2017-08-28PCI: rockchip: Idle inactive PHY(s)Shawn Lin
Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-28PCI: rockchip: Add per-lane PHY supportShawn Lin
We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-24PCI: Convert to using %pOF instead of full_name()Rob Herring
Now that we have a custom printf format specifier, convert users of full_name() to use %pOF instead. This is preparation for removing storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au>
2017-08-16PCI: xilinx: Allow build on MIPS platformsPaul Burton
Allow the xilinx-pcie driver to be built on MIPS platforms which make use of generic PCI drivers rather than legacy MIPS-specific interfaces. This is used on the MIPS Boston development board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16PCI: xilinx: Don't enable config completion interruptsPaul Burton
The Xilinx AXI bridge for PCI Express device provides interrupts indicating the completion of config space accesses. We have previously enabled/unmasked them but do nothing with them besides acknowledge them. Leave the interrupts masked in order to avoid servicing a large number of pointless interrupts during boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16PCI: xilinx: Unify INTx & MSI interrupt decodePaul Burton
The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3Paul Burton
The devicetree binding documentation for the Xilinx NWL PCIe root port bridge shows an example which uses an interrupt-map property to map PCI INTx interrupts to hardware IRQ numbers 1-4. The driver creates an IRQ domain with size 4, which therefore covers the hwirq range 0-3. This means that if we attempt to make use of the INTD interrupt then we're likely to hit a WARN() in irq_domain_associate() because INTD, or hwirw=4, is outside of the range covered by the IRQ domain. irq_domain_associate() will then return -EINVAL and we'll be unable to make use of INTD. Fix this by making use of the pci_irqd_intx_xlate() helper function to translate the 1-4 range used in the DT to a 0-3 range used within the driver, and stop adding 1 to decoded hwirq numbers. Whilst cleaning up INTx handling we make use of the new PCI_NUM_INTX macro & drop the custom INTX definitions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
2017-08-16PCI: xilinx: Translate INTx range to hwirqs 0-3Paul Burton
The pcie-xilinx driver creates an IRQ domain of size 4 for legacy PCI INTx interrupts, which at first glance seems reasonable since there are 4 possible such interrupts. Unfortunately the driver then proceeds to use the range 1-4 as the hwirq numbers for INTA-INTD, causing warnings & broken interrupts when attempting to use INTD/hwirq=4 due to it being beyond the range of the IRQ domain: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:365 irq_domain_associate+0x170/0x220 error: hwirq 0x4 is too large for dummy Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.12.0-rc5-00126-g19e1b3a10aad-dirty #427 Stack : 0000000000000000 0000000000000004 0000000000000006 ffffffff8092c78a 0000000000000061 ffffffff8018bf60 0000000000000000 0000000000000000 ffffffff8088c287 ffffffff80811d18 a8000000ffc60000 ffffffff80926678 0000000000000001 0000000000000000 ffffffff80887880 ffffffff80960000 ffffffff80920000 ffffffff801e6744 ffffffff80887880 a8000000ffc4f8f8 000000000000089c ffffffff8018d260 0000000000010000 ffffffff80811d18 0000000000000000 0000000000000001 0000000000000000 0000000000000000 0000000000000000 a8000000ffc4f840 0000000000000000 ffffffff8042cf34 0000000000000000 0000000000000000 0000000000000000 0000000000040c00 0000000000000000 ffffffff8010d1c8 0000000000000000 ffffffff8042cf34 ... Call Trace: [<ffffffff8010d1c8>] show_stack+0x80/0xa0 [<ffffffff8042cf34>] dump_stack+0xd4/0x110 [<ffffffff8013ea98>] __warn+0xf0/0x108 [<ffffffff8013eb14>] warn_slowpath_fmt+0x3c/0x48 [<ffffffff80196528>] irq_domain_associate+0x170/0x220 [<ffffffff80196bf0>] irq_create_mapping+0x88/0x118 [<ffffffff801976a8>] irq_create_fwspec_mapping+0xb8/0x320 [<ffffffff80197970>] irq_create_of_mapping+0x60/0x70 [<ffffffff805d1318>] of_irq_parse_and_map_pci+0x20/0x38 [<ffffffff8049c210>] pci_fixup_irqs+0x60/0xe0 [<ffffffff8049cd64>] xilinx_pcie_probe+0x28c/0x478 [<ffffffff804e8ca8>] platform_drv_probe+0x50/0xd0 [<ffffffff804e73a4>] driver_probe_device+0x2c4/0x3a0 [<ffffffff804e7544>] __driver_attach+0xc4/0xd0 [<ffffffff804e5254>] bus_for_each_dev+0x64/0xa8 [<ffffffff804e5e40>] bus_add_driver+0x1f0/0x268 [<ffffffff804e8000>] driver_register+0x68/0x118 [<ffffffff801001a4>] do_one_initcall+0x4c/0x178 [<ffffffff808d3ca8>] kernel_init_freeable+0x204/0x2b0 [<ffffffff80730b68>] kernel_init+0x10/0xf8 [<ffffffff80106218>] ret_from_kernel_thread+0x14/0x1c Fix this by making use of the new pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 range suitable for the IRQ domain of size 4, and stop adding 1 to the hwirq number decoded from the interrupt FIFO which is already in the range 0-3. Whilst we're here we switch to using PCI_NUM_INTX rather than the magic number 4, making it clearer what the 4 means. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
2017-08-16PCI: rockchip: Factor out rockchip_pcie_get_phys()Shawn Lin
We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-16PCI: rockchip: Control optional 12v power supplyShawn Lin
Get vpcie12v from DT and control it if available. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: faraday: Use PCI_NUM_INTXPaul Burton
Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: faraday: Fix of_irq_get() error checkSergei Shtylyov
of_irq_get() may return a negative error number as well as 0 on failure, while the driver only checks for 0, blithely continuing with the call to irq_set_chained_handler_and_data() -- that function expects *unsigned int* so should probably do nothing when a large IRQ number resulting from a conversion of a negative error number is passed to it. The driver then probes successfully while being only partly functional... Check for 'irq <= 0' instead and propagate the negative error number to the probe method -- that will allow the deferred probing as well. Fixes: d3c68e0a7e34 ("PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-16PCI: altera: Use size=4 IRQ domain for legacy INTxPaul Burton
The devicetree binding documentation for the Altera PCIe controller shows an example which uses an interrupt-map property to map PCI INTx interrupts to hardware IRQ numbers 1-4. The driver creates an IRQ domain with size 5 in order to cover this range, with hwirq=0 left unused. This patch cleans up this wasted IRQ domain entry, modifying the driver to use an IRQ domain of size 4 which matches the actual number of PCI INTx interrupts. Since the hwirq numbers 1-4 are part of the devicetree binding, and this is considered ABI, we cannot simply change the interrupt-map property to use the range 0-3. Instead we make use of the pci_irqd_intx_xlate() helper function to translate the range 1-4 used at the DT level into the range 0-3 which is now used within the driver, and stop adding 1 to decoded hwirq numbers in altera_pcie_isr(). Whilst cleaning up INTx handling we make use of the new PCI_NUM_INTX macro & drop the custom INTX_NUM definition. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-08-16PCI: altera: Remove unused num_of_vectors variableShawn Lin
The local variable "num_of_vectors" was unused, so remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-08-16PCI: aardvark: Use PCI_NUM_INTXPaul Burton
Switch from using a custom LEGACY_IRQ_NUM macro to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-15PCI: rcar: Fix memory leak when no PCIe card is insertedHarunobu Kurokawa
When no PCIe card is inserted, there is a memory leak as pci_free_resource_list() is not called before returning. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2017-08-15PCI: rcar: Fix error exit pathLorenzo Pieralisi
Commit 90634e854079 ("PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()") converted PCI root bus scan API to the new pci_scan_root_bus_bridge() API; in the process some error paths were not updated correctly which may cause memory leaks. Fix the driver error exit path reinstating the previous correct error exit behaviour. Fixes: 90634e854079 ("PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2017-08-14PCI: vmd: Free up IRQs on suspend pathScott Bauer
Free up the IRQs we request on the suspend path and reallocate them on the resume path. Fixes this error: CPU 111 disable failed: CPU has 9 vectors assigned and there are only 0 available. Error taking CPU111 down: -34 Non-boot CPUs are not disabled Enabling non-boot CPUs ... Signed-off-by: Scott Bauer <scott.bauer@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com>
2017-08-10hyper-v: Globalize vp_indexVitaly Kuznetsov
To support implementing remote TLB flushing on Hyper-V with a hypercall we need to make vp_index available outside of vmbus module. Rename and globalize. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Stephen Hemminger <sthemmin@microsoft.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Haiyang Zhang <haiyangz@microsoft.com> Cc: Jork Loeser <Jork.Loeser@microsoft.com> Cc: K. Y. Srinivasan <kys@microsoft.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Simon Xiao <sixiao@microsoft.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: devel@linuxdriverproject.org Link: http://lkml.kernel.org/r/20170802160921.21791-7-vkuznets@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-08-03PCI: hv: Do not sleep in compose_msi_msg()Stephen Hemminger
The setup of MSI with Hyper-V host was sleeping with locks held. This error is reported when doing SR-IOV hotplug with kernel built with lockdep: BUG: sleeping function called from invalid context at kernel/sched/completion.c:93 in_atomic(): 1, irqs_disabled(): 1, pid: 1405, name: ip 3 locks held by ip/1405: #0: (rtnl_mutex){+.+.+.}, at: [<ffffffff976b10bb>] rtnetlink_rcv+0x1b/0x40 #1: (&desc->request_mutex){+.+...}, at: [<ffffffff970ddd33>] __setup_irq+0xb3/0x720 #2: (&irq_desc_lock_class){-.-...}, at: [<ffffffff970ddd65>] __setup_irq+0xe5/0x720 irq event stamp: 3476 hardirqs last enabled at (3475): [<ffffffff971b3005>] get_page_from_freelist+0x225/0xc90 hardirqs last disabled at (3476): [<ffffffff978024e7>] _raw_spin_lock_irqsave+0x27/0x90 softirqs last enabled at (2446): [<ffffffffc05ef0b0>] ixgbevf_configure+0x380/0x7c0 [ixgbevf] softirqs last disabled at (2444): [<ffffffffc05ef08d>] ixgbevf_configure+0x35d/0x7c0 [ixgbevf] The workaround is to poll for host response instead of blocking on completion. Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-03PCI: vmd: Assign vector zero to all bridgesKeith Busch
We don't want slower IRQ handlers impacting faster devices that happen to be assigned the same VMD interrupt vector. The driver was trying to separate such devices by checking if MSI-X wasn't used, but really we just don't want endpoint devices to share with bridges. Most bridges may use MSI currently, so that criteria happened to work, but newer ones may use MSI-X, so this patch explicitly checks the device type when choosing a vector. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-03PCI: vmd: Reserve IRQ pre-vector for better affinityKeith Busch
The driver has a special purpose for the VMD device's first IRQ, so this one shouldn't be considered for IRQ affinity. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-03PCI: tegra: Explicitly request exclusive reset controlPhilipp Zabel
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com>
2017-08-02PCI: mvebu: Remove unneeded gpiod NULL checkFabio Estevam
The gpiod API checks for NULL descriptors, so there is no need to duplicate the check in the driver. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com
2017-07-31PCI: iproc: Remove unused struct iproc_pcie *pcieShawn Lin
The local variable "pcie" was unused, so remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ray Jui <rjui@broadcom.com>
2017-07-12PCI: rockchip: Check for pci_scan_root_bus_bridge() failure correctlyShawn Lin
pci_scan_root_bus_bridge() returns zero for success, or a negative errno. A typo in ae13cb9b1926 ("PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()") treated zero as a failure. Fix the typo. Fixes: ae13cb9b1926 ("PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2017-07-08Merge tag 'pci-v4.13-changes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add sysfs max_link_speed/width, current_link_speed/width (Wong Vee Khee) - make host bridge IRQ mapping much more generic (Matthew Minter, Lorenzo Pieralisi) - convert most drivers to pci_scan_root_bus_bridge() (Lorenzo Pieralisi) - mutex sriov_configure() (Jakub Kicinski) - mutex pci_error_handlers callbacks (Christoph Hellwig) - split ->reset_notify() into ->reset_prepare()/reset_done() (Christoph Hellwig) - support multiple PCIe portdrv interrupts for MSI as well as MSI-X (Gabriele Paoloni) - allocate MSI/MSI-X vector for Downstream Port Containment (Gabriele Paoloni) - fix MSI IRQ affinity pre/post/min_vecs issue (Michael Hernandez) - test INTx masking during enumeration, not at run-time (Piotr Gregor) - avoid using device_may_wakeup() for runtime PM (Rafael J. Wysocki) - restore the status of PCI devices across hibernation (Chen Yu) - keep parent resources that start at 0x0 (Ard Biesheuvel) - enable ECRC only if device supports it (Bjorn Helgaas) - restore PRI and PASID state after Function-Level Reset (CQ Tang) - skip DPC event if device is not present (Keith Busch) - check domain when matching SMBIOS info (Sujith Pandel) - mark Intel XXV710 NIC INTx masking as broken (Alex Williamson) - avoid AMD SB7xx EHCI USB wakeup defect (Kai-Heng Feng) - work around long-standing Macbook Pro poweroff issue (Bjorn Helgaas) - add Switchtec "running" status flag (Logan Gunthorpe) - fix dra7xx incorrect RW1C IRQ register usage (Arvind Yadav) - modify xilinx-nwl IRQ chip for legacy interrupts (Bharat Kumar Gogada) - move VMD SRCU cleanup after bus, child device removal (Jon Derrick) - add Faraday clock handling (Linus Walleij) - configure Rockchip MPS and reorganize (Shawn Lin) - limit Qualcomm TLP size to 2K (hardware issue) (Srinivas Kandagatla) - support Tegra MSI 64-bit addressing (Thierry Reding) - use Rockchip normal (not privileged) register bank (Shawn Lin) - add HiSilicon Kirin SoC PCIe controller driver (Xiaowei Song) - add Sigma Designs Tango SMP8759 PCIe controller driver (Marc Gonzalez) - add MediaTek PCIe host controller support (Ryder Lee) - add Qualcomm IPQ4019 support (John Crispin) - add HyperV vPCI protocol v1.2 support (Jork Loeser) - add i.MX6 regulator support (Quentin Schulz) * tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (113 commits) PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support PCI: Add DT binding for Sigma Designs Tango PCIe controller PCI: rockchip: Use normal register bank for config accessors dt-bindings: PCI: Add documentation for MediaTek PCIe PCI: Remove __pci_dev_reset() and pci_dev_reset() PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done() PCI: xilinx: Make of_device_ids const PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts PCI: vmd: Move SRCU cleanup after bus, child device removal PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000 PCI: versatile: Add local struct device pointers PCI: tegra: Do not allocate MSI target memory PCI: tegra: Support MSI 64-bit addressing PCI: rockchip: Use local struct device pointer consistently PCI: rockchip: Check for clk_prepare_enable() errors during resume MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer PCI: rockchip: Configure RC's MPS setting PCI: rockchip: Reconfigure configuration space header type PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses() PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu() ...
2017-07-07Merge branch 'pci/host-tango' into nextBjorn Helgaas
* pci/host-tango: PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support PCI: Add DT binding for Sigma Designs Tango PCIe controller Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile
2017-07-07PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge supportMarc Gonzalez
This driver is required to work around several hardware bugs in the PCIe controller. The SMP8759 does not support legacy interrupts or IO space. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [bhelgaas: add CONFIG_BROKEN dependency, various cleanups] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-04Merge branch 'pci/host-xilinx' into nextBjorn Helgaas
* pci/host-xilinx: PCI: xilinx: Make of_device_ids const PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts
2017-07-04Merge branch 'pci/host-vmd' into nextBjorn Helgaas
* pci/host-vmd: PCI: vmd: Move SRCU cleanup after bus, child device removal PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000
2017-07-04Merge branch 'pci/host-versatile' into nextBjorn Helgaas
* pci/host-versatile: PCI: versatile: Add local struct device pointers
2017-07-04Merge branch 'pci/host-tegra' into nextBjorn Helgaas
* pci/host-tegra: PCI: tegra: Do not allocate MSI target memory PCI: tegra: Support MSI 64-bit addressing
2017-07-04Merge branch 'pci/host-rockchip' into nextBjorn Helgaas
* pci/host-rockchip: PCI: rockchip: Use normal register bank for config accessors PCI: rockchip: Use local struct device pointer consistently PCI: rockchip: Check for clk_prepare_enable() errors during resume MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer PCI: rockchip: Configure RC's MPS setting PCI: rockchip: Reconfigure configuration space header type PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses() PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu() PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu() PCI: rockchip: Control vpcie0v9 for system PM
2017-07-04Merge branch 'pci/host-rcar' into nextBjorn Helgaas
* pci/host-rcar: PCI: rcar-gen2: Make of_device_ids const PCI: rcar: Use proper name for the R-Car SoC
2017-07-04Merge branch 'pci/host-mediatek' into nextBjorn Helgaas
* pci/host-mediatek: dt-bindings: PCI: Add documentation for MediaTek PCIe PCI: mediatek: Add MediaTek PCIe host controller support
2017-07-03PCI: rockchip: Use normal register bank for config accessorsShawn Lin
Rockchip's RC has two banks of registers for the root port: a normal bank that is strictly compatible with the PCIe spec, and a privileged bank that can be used to change RO bits of root port registers. When probing the RC driver, we use the privileged bank to do some basic setup work as some RO bits are hw-inited to wrong value. But we didn't change to the normal bank after probing the driver. This leads to a serious problem when the PME code tries to clear the PME status by writing PCI_EXP_RTSTA_PME to the register of PCI_EXP_RTSTA. Per PCIe 3.0 spec, section 7.8.14, the PME status bit is RW1C. So the PME code is doing the right thing to clear the PME status but we find the RC doesn't clear it but actually setting it to one. So finally the system trap in pcie_pme_work_fn() as PCI_EXP_RTSTA_PME is true now forever. This issue can be reproduced by booting kernel with pci=nomsi. Use the normal register bank for the PCI config accessors. The privileged bank is used only internally by this driver. Fixes: e77f847d ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Brian Norris <briannorris@chromium.org>
2017-07-03Merge branch 'pci/host-hv' into nextBjorn Helgaas
* pci/host-hv: PCI: hv: Use vPCI protocol version 1.2 PCI: hv: Add vPCI version protocol negotiation PCI: hv: Temporary own CPU-number-to-vCPU-number infra PCI: hv: Use page allocation for hbus structure PCI: hv: Fix comment formatting and use proper integer fields
2017-07-03Merge branch 'pci/host-faraday' into nextBjorn Helgaas
* pci/host-faraday: PCI: faraday: Add clock handling PCI: faraday: Add clock bindings
2017-07-02PCI: xilinx: Make of_device_ids constArvind Yadav
of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. File size before: text data bss dec hex filename 195 600 0 795 31b drivers/pci/host/pcie-xilinx.o File size after constify xilinx_pcie_of_match: text data bss dec hex filename 595 184 0 779 30b drivers/pci/host/pcie-xilinx.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: xilinx-nwl: Modify IRQ chip for legacy interruptsBharat Kumar Gogada
- Add spinlock for protecting legacy mask register - Few wifi end points which only support legacy interrupts, performs hardware reset functionalities after disabling interrupts by invoking disable_irq() and then re-enable using enable_irq(), they enable hardware interrupts first and then virtual IRQ line later. - The legacy IRQ line goes low only after DEASSERT_INTx is received. As the legacy IRQ line is high immediately after hardware interrupts are enabled but virq of EP is still in disabled state and EP handler is never executed resulting no DEASSERT_INTx. If dummy IRQ chip is used, interrupts are not masked and system hangs with CPU stall. - Add IRQ chip functions instead of dummy IRQ chip for legacy interrupts. - Legacy interrupts are level sensitive, so using handle_level_irq() is more appropriate as it is masks interrupts until Endpoint handles interrupts and unmasks interrupts after Endpoint handler is executed. - Legacy interrupts are level triggered, virtual IRQ line of EndPoint shows as edge in /proc/interrupts. - Set IRQ flags of virtual IRQ line of EP to level triggered at the time of mapping. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: vmd: Move SRCU cleanup after bus, child device removalJon Derrick
Recent __call_srcu() changes have exposed that we need to cleanup SRCU structures after pci_stop_root_bus() calls into vmd_msi_free(). Fixes: 3906b91844d6 ("PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCU") Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com> Cc: <stable@vger.kernel.org> # 4.11
2017-07-02PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000Bjorn Helgaas
VMD domains are allocated starting at 0x10000, not 0x1000 as the comment said. Correct the comment and add a reference to the ACPI spec for _SEG. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
2017-07-02PCI: versatile: Add local struct device pointersBjorn Helgaas
Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: tegra: Do not allocate MSI target memoryThierry Reding
The PCI host bridge found on Tegra SoCs doesn't require the MSI target address to be backed by physical system memory. Writes are intercepted within the controller and never make it to the memory pointed to. Since no actual system memory is required, remove the allocation of a single page and hardcode the MSI target address with a special address that maps to the last 4 KiB page within the range that is reserved for system memory and memory-mapped I/O in the FPCI address map. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2017-07-02PCI: tegra: Support MSI 64-bit addressingThierry Reding
The MSI target address can reside beyond the 32-bit boundary on devices with more than 2 GiB of system memory. The PCI host bridge on Tegra can easily support 64-bit addresses, so make sure to pass the upper 32 bits of the target address to endpoints when allocating MSI entries. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2017-07-02PCI: rockchip: Use local struct device pointer consistentlyShawn Lin
We have a local "struct device *dev" in rockchip_pcie_probe(). Use it consistently throughout the function. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Check for clk_prepare_enable() errors during resumeArvind Yadav
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02PCI: rockchip: Configure RC's MPS settingShawn Lin
The default value of MPS for RC is 128 bytes, but actually it could support 256 bytes. So this patch fixes this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Reconfigure configuration space header typeShawn Lin
Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1 configuration space header should be used when accessing PCIe switch. So we need to reconfigure the header according to the bus number we are accessing. Otherwise we could not visit the buses behind the switch. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 14:47:54 +0000