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path: root/drivers/net/wireless/ath/ath11k/pci.c
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2021-11-22ath11k: add CE and ext IRQ flag to indicate irq_handlerCarl Huang
This change adds two flags to indicate whether IRQ handler for CE and DP can be called. This is because in one MSI vector case, interrupt is not disabled in hif_stop and hif_irq_disable. Otherwise, MHI interrupt is disabled too. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Signed-off-by: Baochen Qiang <bqiang@codeaurora.org> Link: https://lore.kernel.org/r/20211026041646.5060-1-bqiang@codeaurora.org
2021-11-22ath11k: get msi_data again after request_irq is calledCarl Huang
The reservation mode of interrupts in kernel assigns a dummy vector when the interrupt is allocated and assigns a real vector when the request_irq is called. The reservation mode helps to ease vector pressure when devices with a large amount of queues/interrupts are initialized, but only a minimal subset of those queues/interrupts is actually used. So on reservation mode, the msi_data may change after request_irq is called, so ath11k reads msi_data again after request_irq is called, and then the correct msi_data is programmed into QCA6390 hardware components. Without this change, spurious interrupt occurs in case of one MSI vector. When VT-d in BIOS is enabled and ath11k can get 32 MSI vectors, ath11k always get the same msi_data before and after request_irq, that's why this change is only required when one MSI vector is to be supported. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20211026041636.5008-1-bqiang@codeaurora.org
2021-11-19ath11k: add hw_param for wakeup_mhiSeevalamuthu Mariappan
Wakeup mhi is needed before pci_read/write only for QCA6390 and WCN6855. Since wakeup & release mhi is enabled for all hardwares, below mhi assert is seen in QCN9074 when doing 'rmmod ath11k_pci': Kernel panic - not syncing: dev_wake != 0 CPU: 2 PID: 13535 Comm: procd Not tainted 4.4.60 #1 Hardware name: Generic DT based system [<80316dac>] (unwind_backtrace) from [<80313700>] (show_stack+0x10/0x14) [<80313700>] (show_stack) from [<805135dc>] (dump_stack+0x7c/0x9c) [<805135dc>] (dump_stack) from [<8032136c>] (panic+0x84/0x1f8) [<8032136c>] (panic) from [<80549b24>] (mhi_pm_disable_transition+0x3b8/0x5b8) [<80549b24>] (mhi_pm_disable_transition) from [<80549ddc>] (mhi_power_down+0xb8/0x100) [<80549ddc>] (mhi_power_down) from [<7f5242b0>] (ath11k_mhi_op_status_cb+0x284/0x3ac [ath11k_pci]) [E][__mhi_device_get_sync] Did not enter M0 state, cur_state:RESET pm_state:SHUTDOWN Process [E][__mhi_device_get_sync] Did not enter M0 state, cur_state:RESET pm_state:SHUTDOWN Process [E][__mhi_device_get_sync] Did not enter M0 state, cur_state:RESET pm_state:SHUTDOWN Process [<7f5242b0>] (ath11k_mhi_op_status_cb [ath11k_pci]) from [<7f524878>] (ath11k_mhi_stop+0x10/0x20 [ath11k_pci]) [<7f524878>] (ath11k_mhi_stop [ath11k_pci]) from [<7f525b94>] (ath11k_pci_power_down+0x54/0x90 [ath11k_pci]) [<7f525b94>] (ath11k_pci_power_down [ath11k_pci]) from [<8056b2a8>] (pci_device_shutdown+0x30/0x44) [<8056b2a8>] (pci_device_shutdown) from [<805cfa0c>] (device_shutdown+0x124/0x174) [<805cfa0c>] (device_shutdown) from [<8033aaa4>] (kernel_restart+0xc/0x50) [<8033aaa4>] (kernel_restart) from [<8033ada8>] (SyS_reboot+0x178/0x1ec) [<8033ada8>] (SyS_reboot) from [<80301b80>] (ret_fast_syscall+0x0/0x34) Hence, disable wakeup/release mhi using hw_param for other hardwares. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01060-QCAHKSWPL_SILICONZ-1 Fixes: a05bd8513335 ("ath11k: read and write registers below unwindowed address") Signed-off-by: Seevalamuthu Mariappan <quic_seevalam@quicinc.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1636702019-26142-1-git-send-email-quic_seevalam@quicinc.com
2021-11-17ath11k: add string type to search board data in board-2.bin for WCN6855Wen Gong
Currently ath11k only support string type with bus, chip id and board id such as "bus=ahb,qmi-chip-id=1,qmi-board-id=4" for ahb bus chip and "bus=pci,qmi-chip-id=0,qmi-board-id=255" for PCIe bus chip in board-2.bin. For WCN6855, it is not enough to distinguish all different chips. This is to add a new string type which include bus, chip id, board id, vendor, device, subsystem-vendor and subsystem-device for WCN6855. ath11k will first load board-2.bin and search in it for the board data with the above parameters, if matched one board data, then download it to firmware, if not matched any one, then ath11k will download the file board.bin to firmware. Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Signed-off-by: Wen Gong <quic_wgong@quicinc.com> Signed-off-by: Jouni Malinen <quic_jouni@quicinc.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20211111065340.20187-1-quic_wgong@quicinc.com
2021-10-11ath11k: Handle MSI enablement during rmmod and SSRBaochen Qiang
When doing "rmmod ath11k_pci", ath11k performs global SOC reset and MHI reset, where 0 address access is captured by IOMMU. See log below: ... [ 133.953860] ath11k_pci 0000:02:00.0: setting mhi state: DEINIT(1) [ 133.959714] ath11k_pci 0000:02:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x000a address=0x0 flags=0x0020] [ 133.973854] ath11k_pci 0000:02:00.0: MHISTATUS 0xff04 [ 133.974095] ath11k_pci 0000:02:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x000a address=0x0 flags=0x0020] ... This issue is also observed in SSR process, cause a similar sequence as above is performed. Such an invalid access occurs because, during rmmod or SSR, MSI address is cleared but HW MSI functionality not disabled, thus HW target is able to raise an MSI transaction with 0 as MSI address. So it can be fixed by simply disabling MSI before reset. For SSR, since MSI functionality is still needed after target is brought back, we need to reenable it. Also change naming of some interfaces related. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Signed-off-by: Baochen Qiang <bqiang@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210913180246.193388-5-jouni@codeaurora.org
2021-09-28ath11k: Fix inaccessible debug registersBaochen Qiang
Current code clears debug registers after SOC global reset performed in ath11k_pci_sw_reset. However at that time those registers are not accessible due to reset, thus they are actually not cleared at all. For WCN6855, it may cause target fail to initialize. This issue can be fixed by moving clear action ahead. In addition, on some specific platforms, need to add delay to wait those registers to become accessible. Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Signed-off-by: Baochen Qiang <bqiang@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210913180246.193388-3-jouni@codeaurora.org
2021-07-02ath: switch from 'pci_' to 'dma_' APIChristophe JAILLET
The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below. While at it, some 'dma_set_mask()/dma_set_coherent_mask()' have been updated to a much less verbose 'dma_set_mask_and_coherent()'. @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/9150bd6cde9ad592aff8ee3ad94dffa90b004e89.1624720959.git.christophe.jaillet@wanadoo.fr
2021-06-19ath11k: Enable QCN9074 deviceAnilkumar Kolli
The issues mentioned in commit 4e80946197a8 ("ath11k: add qcn9074 pci device support") are fixed in firmware. This patch enables QCN9074 device. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1-01838-QCAHKSWPL_SILICONZ-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210615211348.92168-1-jouni@codeaurora.org
2021-06-12ath11k: don't call ath11k_pci_set_l1ss for WCN6855Baochen Qiang
For QCA6390, one PCI related clock drifts sometimes, and it makes PCI link difficult to quit L1ss. Current implementation fixed this by configuring some related regs using ath11k_pci_fix_l1ss. WCN6855 does not have this clock drift problem, so no need to set these regs. Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Baochen Qiang <bqiang@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210511162214.29475-8-jouni@codeaurora.org
2021-06-12ath11k: add support for WCN6855Baochen Qiang
This patch is to add support for WCN6855. For station mode, WCN6855 is able to connect to an AP, and ping works well. For AP mode, hostapd is able to bringup an SAP interface with WCN6855, a normal station can connect to this AP and ping works well. Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Baochen Qiang <bqiang@codeaurora.org> Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210511162214.29475-7-jouni@codeaurora.org
2021-02-17ath11k: add qcn9074 pci device supportAnilkumar Kolli
QCN9074 is PCI based 11ax radio. - has 2G/5G/6G variants. - has NSS 2x2 and 4x4 variants. QCN9074 uses 45MB of HOST DDR memory, target requests host memory in segments, each segment is of 2MB size and is physcial contiguous and use static window configuration. Currently there are still two issues with QCN9074, see below. So we don't add QCN9074 PCI id yet to make sure the driver is loaded. The id will be added only after the issues are fixed. Issue 1: ath11k_pci 0000:06:00.0: qmi failed memory request, err = -110 ath11k_pci 0000:06:00.0: qmi failed to respond fw mem req:-110 Issue 2: ath11k_pci 0000:06:00.0: firmware crashed: MHI_CB_SYS_ERROR ath11k_pci 0000:06:00.0: qmi failed set mode request, mode: 0, err = -110 ath11k_pci 0000:06:00.0: qmi failed to send wlan fw mode:-110 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-12-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: add extended interrupt support for QCN9074Karthikeyan Periyasamy
Update the specific hw ring mask for QCN9074. Update the timestamp information while processing DP and CE interrupts. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org> Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-11-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: add CE interrupt support for QCN9074Karthikeyan Periyasamy
Define host CE configuration for QCN9074 since the max CE count is six. Available MSI interrupt is five so cannot able to map the ce_id directly for the msi_data_idx. Added get_ce_msi_idx ops in ath11k_hif_ops to get the CE MSI idx which is used to initialize the CE ring. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org> Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-10-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: add data path support for QCN9074Karthikeyan Periyasamy
hal rx descriptor is different for QCN9074 target type. since rx_msdu_end, rx_msdu_start, rx_mpdu_start elements are in different placement/alignment. In order to have generic data path, introduce platform specific hal rx descriptor access ops in ath11k_hw_ops. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org> Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-9-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: add hal support for QCN9074Karthikeyan Periyasamy
Define the hal ring address and ring meta descriptor mask for QCN9074. Move the platform specific address to the ath11k_hw_regs. Define tx_mesh_enable ops in ath11k_hw_ops since its accessing platform specific TCL descriptor. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org> Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-8-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: add static window support for register accessKarthikeyan Periyasamy
Three window slots can be configure. First window slot dedicate for dynamic selection and remaining two slots dedicate for static selection. To optimise the window selection, frequent registers (UMAC, CE) are configure in static window slot. so that we minimise the window selection. Other registers are configure in dynamic window slot. Get the window start address from the respective offset and access the read/write register. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org> Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-7-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: Move qmi service_ins_id to hw_paramsAnilkumar Kolli
qmi service_ins_id is unique for QCA6390 and QCN9074, this is needed for adding QCN9074 support. No functional changes. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-3-git-send-email-akolli@codeaurora.org
2021-02-17ath11k: Refactor ath11k_msi_configAnilkumar Kolli
Move ath11k_msi_config to array of structures to add multiple pci devices support. No functional changes. Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1612946530-28504-2-git-send-email-akolli@codeaurora.org
2021-02-11ath11k: pci: remove experimental warningKalle Valo
I have received feedback that QCA6390 PCI support is working for many, and I'm also using QCA6390 on my daily driver^Hlaptop. While there are issues still to be resolved it's not really experimental anymore, so remove the experimental warning from driver initialisation. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1613040697-20289-1-git-send-email-kvalo@codeaurora.org
2021-01-11Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.gitKalle Valo
ath.git patches for v5.12. Major changes: ath9k * more robust encryption key cache management
2020-12-18ath11k: pci: remove unnecessary mask in ath11k_pci_enable_ltssm()Kalle Valo
0x10 is a leftover and unnecessary, GCC_GCC_PCIE_HOT_RST_VAL is already defined to 0x10. No functional changes, compile tested only. Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1608143051-5386-1-git-send-email-kvalo@codeaurora.org
2020-12-18ath11k: pci: disable ASPM L0sLs before downloading firmwareCarl Huang
Sometimes QCA6390 doesn't switch to amss state as device enters L1ss state, so disable L0sL1s during firmware downloading. Driver recovers the ASPM to default value in start callback or powerdown callback. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1608218530-15426-1-git-send-email-kvalo@codeaurora.org
2020-12-17ath11k: Fix ath11k_pci_fix_l1ss()Dan Carpenter
All these conditions are reversed so presumably most of the function is dead code. This caused a spurious warning: [ 95.734922] ath11k_pci 0000:06:00.0: failed to set sysclk: 0 Fixes: 0699940755e9 ("ath11k: pci: fix L1ss clock unstable problem") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/X9nGDHiTh+Z+asDy@mwanda
2020-12-12ath11k: implement suspend for QCA6390 PCI devicesCarl Huang
Now that all the needed pieces are in place implement suspend support QCA6390 PCI devices. All other devices will return -EOPNOTSUPP during suspend. The suspend is implemented by switching the firmware to WoW mode during suspend, so the firmware will be running on low power mode while host is in suspend. At the moment we are not able to shutdown and fully power off the device due to bugs in MHI subsystem, so WoW mode is a workaround for the time being. During suspend we enable WoW mode, disable CE irq and DP irq, then put MHI to suspend state. During resume, driver resumes MHI firstly, then enables CE irq and dp IRQ, and sends WoW wakeup command to firmware. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607708150-21066-11-git-send-email-kvalo@codeaurora.org
2020-12-12ath11k: hif: add ce irq enable and disable functionsCarl Huang
Add ce irq enable and disable hif layer functions, so core module can enable enable them without cleaning pipe and refilling pipe. Needed for suspend. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607708150-21066-10-git-send-email-kvalo@codeaurora.org
2020-12-12ath11k: pci: read select_window register to ensure write is finishedCarl Huang
Just when resume from WoW, the write to select_window doesn't take effect immediately, so read the register again to ensure the write operation is finished. Another change is to reset select_window to ZERO because this register isn't restored after WoW, so the content of this register becomes ZERO too. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607708150-21066-4-git-send-email-kvalo@codeaurora.org
2020-12-12ath11k: hif: implement suspend and resume functionsCarl Huang
For suspend support add suspend and resume to HIF layer. These ops are optional and, for example, AHB bus driver does not need to implement these. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607708150-21066-3-git-send-email-kvalo@codeaurora.org
2020-12-12ath11k: pci: disable VDD4BLOWCarl Huang
It's recommended to disable VDD4BLOW during initialisation. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607609124-17250-6-git-send-email-kvalo@codeaurora.org
2020-12-12ath11k: pci: fix L1ss clock unstable problemCarl Huang
For QCA6390, one PCI related clock drifts sometimes, and it makes PCI link difficult to quit L1ss. Fix it by writing some registers which are known to fix the problem. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607609124-17250-5-git-send-email-kvalo@codeaurora.org
2020-12-12ath11k: pci: fix hot reset stability issuesCarl Huang
For QCA6390, host needs to reset some registers before MHI power up to fix PCI link unstable issue if hot reset happened. Also clear all pending interrupts during power up. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1607609124-17250-4-git-send-email-kvalo@codeaurora.org
2020-12-09ath11k: fix rmmod failure if qmi sequence failsAnilkumar Kolli
QMI sequence fails if caldata file is not available. It is observed that 'rmmod ath11k' fails if qmi message fails. With this patch rmmod/insmod is working. Logs: Direct firmware load for IPQ8074/caldata.bin failed with error -2 Falling back to user helper qmi failed to load CAL: IPQ8074/caldata.bin qmi failed to load board data file:-11 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00009-QCAHKSWPL_SILICONZ-1 Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01699-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1606916215-24643-1-git-send-email-akolli@codeaurora.org
2020-12-08ath11k: pci: add MODULE_FIRMWARE macrosDevin Bayer
I am trying to get the ath11k driver to work with VyOS and during the build it tries to discover the firmware blobs which drivers require. This doesn't work with ath11k because it doesn't use the MODULE_FIRMWARE macro. This patch fixes that. Signed-off-by: Devin Bayer <dev@doubly.so> [kvalo@codeaurora.org: cleanup commit log, move to pci.c] Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201202182705.dhkml4nb4rf2vwav@orac
2020-12-07ath11k: add 64bit check before reading msi high addrAnilkumar Kolli
In QCN9074 ath11k boot, firmware crash is observed in 64-bit builds and is due to wrong 64 bit MSI address size. This patch fixes the firmware crash. Read msi high addr if 64-bit addresses allowed on MSI. Tested-On: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r1-00026-QCAHKSWPL_SILICONZ-2 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1606199334-18206-1-git-send-email-akolli@codeaurora.org
2020-11-07ath11k: convert tasklets to use new tasklet_setup() APIAllen Pais
In preparation for unconditionally passing the struct tasklet_struct pointer to all tasklet callbacks, switch to using the new tasklet_setup() and from_tasklet() to pass the tasklet pointer explicitly. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Allen Pais <apais@linux.microsoft.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201007103309.363737-4-allen.lkml@gmail.com
2020-10-01ath11k: enable shadow register configuration and accessCarl Huang
To enable shadow register access, host needs to pass shadow register configuration to firmware via qmi message. Host also needs to update ring's HP or TP address to shadow register address. The write operation to shadow register will be forwarded to target register by hardware automatically, and the write operation to shadow register is permitted even when the target is in power save or sleep mode. Update the shadow config whenever power up happens. This feature is controlled by hw parameter supports_shadow_regs which is only enabled for QCA6390. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1601544890-13450-3-git-send-email-kvalo@codeaurora.org
2020-10-01ath11k: read and write registers below unwindowed addressCarl Huang
For QCA6390, host can read and write registers below unwindowed address directly without programming the window register. For registers below bar0 + 4k - 32, host can read and write regardless of the power save state. Shadow registers are located below bar0 + 4K - 32. Before MHI power up, there is no need to wakeup MHI so ini_done is added to indicate it. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1601544890-13450-2-git-send-email-kvalo@codeaurora.org
2020-10-01ath11k: pci: fix rmmod crashCarl Huang
For QCA6390 we first need to call free_irq() and only then disable_msi(). Otherwise a kernel BUG below will happen. Also free core, hal_srng and ce resources during ath11k_pci_remove(). [ 1089.425506] ------------[ cut here ]------------ [ 1089.425510] kernel BUG at drivers/pci/msi.c:375! [ 1089.425514] invalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC PTI [ 1089.425517] CPU: 1 PID: 20539 Comm: rmmod Not tainted 5.9.0-rc5-wt-ath+ #198 [ 1089.425519] Hardware name: Intel(R) Client Systems NUC8i7HVK/NUC8i7HVB, BIOS HNKBLi70.86A.0049.2018.0801.1601 08/01/2018 [ 1089.425523] RIP: 0010:free_msi_irqs+0x184/0x1b0 [ 1089.425526] Code: 14 85 c0 0f 84 cc fe ff ff 31 ed eb 0f 83 c5 01 39 6b 14 0f 86 bc fe ff ff 8b 7b 10 01 ef e8 c3 01 bf ff 48 83 78 70 00 74 e3 <0f> 0b 49 8d b5 b0 00 00 0 [ 1089.425528] RSP: 0018:ffffb128c0cf7dd0 EFLAGS: 00010282 [ 1089.425530] RAX: ffff947d67549000 RBX: ffff947cd2d25200 RCX: 0000000000000000 [ 1089.425532] RDX: ffff947d94a6f928 RSI: ffff947d94a6fa18 RDI: 0000000000000099 [ 1089.425533] RBP: 0000000000000000 R08: ffff947d67549000 R09: ffffffff86670050 [ 1089.425535] R10: 0000000000000000 R11: 0000000000000000 R12: ffff947d96c194f0 [ 1089.425537] R13: ffff947d96c19000 R14: 0000000000000000 R15: ffffffffc0225250 [ 1089.425539] FS: 00007f97c44ed700(0000) GS:ffff947d9c200000(0000) knlGS:0000000000000000 [ 1089.425541] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1089.425543] CR2: 00007f97c408d701 CR3: 0000000192bc0006 CR4: 00000000003706e0 [ 1089.425544] Call Trace: [ 1089.425549] ath11k_pci_remove+0x2b/0x90 [ath11k_pci] [ 1089.425553] pci_device_remove+0x36/0x90 [ 1089.425556] __device_release_driver+0x16c/0x220 [ 1089.425559] driver_detach+0xcf/0x110 [ 1089.425561] bus_remove_driver+0x4d/0xa2 [ 1089.425564] pci_unregister_driver+0x25/0xa0 [ 1089.425568] __do_sys_delete_module+0x163/0x240 [ 1089.425571] ? trace_hardirqs_on+0x1c/0x100 [ 1089.425575] do_syscall_64+0x33/0x40 [ 1089.425577] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 1089.425579] RIP: 0033:0x7f97c401d9e7 [ 1089.425581] Code: 73 01 c3 48 8b 0d b1 c4 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 b8 b0 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c [ 1089.425583] RSP: 002b:00007fff1e0fb728 EFLAGS: 00000206 ORIG_RAX: 00000000000000b0 [ 1089.425585] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f97c401d9e7 [ 1089.425587] RDX: 000000000000000a RSI: 0000000000000800 RDI: 00005585aad022e8 [ 1089.425589] RBP: 00005585aad02280 R08: 0000000000000000 R09: 1999999999999999 [ 1089.425591] R10: 0000000000000883 R11: 0000000000000206 R12: 00007fff1e0fb940 [ 1089.425592] R13: 00007fff1e0fd917 R14: 0000000000000000 R15: 00005585aad02280 [ 1089.425596] Modules linked in: ath11k_pci(-) ath11k qmi_helpers qrtr_mhi mhi qrtr ns nvme nvme_core [last unloaded: mhi] [ 1089.425603] ---[ end trace 2a81926cc0708a38 ]--- Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1601463073-12106-3-git-send-email-kvalo@codeaurora.org
2020-10-01ath11k: pci: check TCSR_SOC_HW_VERSIONKalle Valo
There are different versions of QCA6390. Check TCSR_SOC_HW_VERSION to make sure that the device is hw2.0, all the rest are unsupported. This needs to be checked after ath11k_pci_claim() so move the whole switch choosing hw_ver. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1601399736-3210-5-git-send-email-kvalo@codeaurora.org
2020-09-11ath11k: move target ce configs to hw_paramsAnilkumar Kolli
Move target CE config and target CE service config to hw_params. No functional changes. Tested on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00009-QCAHKSWPL_SILICONZ-1 Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/010101746cb685d9-6bedeccb-29a1-4d32-8664-fcfe7d105f4a-000000@us-west-2.amazonses.com
2020-08-31ath11k: fix missing error check on call to ath11k_pci_get_user_msi_assignmentColin Ian King
The return error check on the call to ath11k_pci_get_user_msi_assignment is missing. If an error does occur, num_vectors is still set to zero and later on a division by zero can occur when variable vector is being calculated. Fix this by adding an error check after the call. Addresses-Coverity: ("Division or modulo by zero") Fixes: d4ecb90b3857 ("ath11k: enable DP interrupt setup for QCA6390") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200819111452.52419-1-colin.king@canonical.com
2020-08-18ath11k: reset MHI during power down and power upCarl Huang
For QCA6390, normal power up and power down can't bring MHI to a workable state. This happens especially in warm reboot and rmmod and insmod. Host needs to write a few registers to bring MHI to normal state. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Carl Huang <cjhuang@codeauroro.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597555891-26112-10-git-send-email-kvalo@codeaurora.org
2020-08-18ath11k: enable DP interrupt setup for QCA6390Carl Huang
QCA6390 uses MSI interrupt, so need to configure msi_add and msi_data to dp srngs. As there are so many DP srngs, so need to group them. Each group shares one MSI interrupt. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597555891-26112-2-git-send-email-kvalo@codeaurora.org
2020-08-18ath11k: disable CE interrupt before hif startCarl Huang
Disable CE interrupt otherwise interrupt may come before host initialized related context. This also fixes unbalanced interrupt enablement. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597576599-8857-9-git-send-email-kvalo@codeaurora.org
2020-08-18ath11k: ce: remove CE_COUNT() macroKalle Valo
This macro is evil as it's accesses ab variable in a hidden way. It's better for readibility to access ab->hw_params.ce_count directly. This is done in a separate patch to keep the patches simple. No functional changes. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597576599-8857-6-git-send-email-kvalo@codeaurora.org
2020-08-18ath11k: ce: support different CE configurationsCarl Huang
QCA6390 uses only 9 Copy Engines while IPQ8074 may use 12, make it possible to change CE configuration dynamically via hw_params. The defines for host_ce_config_wlan and CE_COUNT are temporary solutions, they will be removed in the following patches to keep things simple. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597576599-8857-4-git-send-email-kvalo@codeaurora.org
2020-08-17ath11k: setup ce tasklet for control pathGovind Singh
CE srng is used for control path and CE srng processing is done using tasklet bottom half. Setup ce tasklet initialization and scheduling for control path. Needed for PCI support. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597389030-13887-7-git-send-email-kvalo@codeaurora.org
2020-08-17ath11k: configure copy engine msi address in CE srngGovind Singh
Fill msi base address and msi data to be programmed in CE srang. This is used by the srng to generate the msi interrupt. Needed for PCI support. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597389030-13887-6-git-send-email-kvalo@codeaurora.org
2020-08-17ath11k: pci: add read32() and write32() hif operationsGovind Singh
Add support for bus read/write/window selection operations for reading hardware memory. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597389030-13887-5-git-send-email-kvalo@codeaurora.org
2020-08-17ath11k: fill appropriate QMI service instance id for QCA6390Govind Singh
QMI service instance id is used for qmi service lookup, IPQ8074 and QCA6390 uses different instance id for service lookup. Fill appropriate QMI service instance id for respective targets. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597389030-13887-4-git-send-email-kvalo@codeaurora.org
2020-08-17ath11k: add board file support for PCI devicesGovind Singh
PCI devices like QCA6390 load the board file differently, add support for that and the method is chosen using bus_params variables. Add support to create board name for different targets. This board name is used to parse the board data from board-2.bin for ahb/pci based targets. As struct target_mem_chunk::vaddr was changed from 'u32' to 'u32 *' in ath11k_qmi_assign_target_mem_chunk() vaddr assignments were changed to NULL to avoid a compilation warning. IPQ8074 does not use the vaddr field for anything so that change does not affect functionality. At the moment this only supports board files with BIN type. Support for ELF type, which seems to be more popular on QCA6390 devices, needs to be added later. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597389030-13887-3-git-send-email-kvalo@codeaurora.org
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