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path: root/drivers/net/phy
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2024-02-21net: phy: marvell-88q2xxx: make mv88q2xxx_config_aneg genericDimitri Fedrau
Marvell 88Q2xxx devices follow the same scheme, after configuration they need a soft reset. Soft resets differ between devices, so we use the .soft_reset callback instead of creating .config_aneg callbacks for each device. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-11-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: marvell-88q2xxx: add cable test supportDimitri Fedrau
Add cable test support for Marvell 88Q222x devices. Reported distance granularity is 1m. 1m cable, open: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Open Circuit Pair A, fault length: 1.00m 1m cable, shorted: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Short within Pair Pair A, fault length: 1.00m 6m cable, open: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Open Circuit Pair A, fault length: 6.00m 6m cable, shorted: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Short within Pair Pair A, fault length: 6.00m Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240218075753.18067-10-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: marvell-88q2xxx: add support for temperature sensorDimitri Fedrau
Marvell 88q2xxx devices have an inbuilt temperature sensor. Add hwmon support for this sensor. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-9-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: marvell-88q2xxx: add suspend / resume opsDimitri Fedrau
Add suspend/resume ops for Marvell 88Q2xxx devices. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-8-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: marvell-88q2xxx: add interrupt support for link detectionDimitri Fedrau
Added .config_intr and .handle_interrupt callbacks. Whenever the link goes up or down an interrupt will be triggered. Interrupts are configured separately for 100/1000BASET1. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-7-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: marvell-88q2xxx: add driver for the Marvell 88Q2220 PHYDimitri Fedrau
Add a driver for the Marvell 88Q2220. This driver allows to detect the link, switch between 100BASE-T1 and 1000BASE-T1 and switch between master and slave mode. Autonegotiation is supported. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-6-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: marvell-88q2xxx: fix typosDimitri Fedrau
Rename mv88q2xxxx_get_sqi to mv88q2xxx_get_sqi and mv88q2xxxx_get_sqi_max to mv88q2xxx_get_sqi_max. Fix linebreaks and use everywhere hexadecimal numbers written with lowercase letters instead of mixing it up. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-5-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: c45: detect 100/1000BASE-T1 linkmode advertisementsDimitri Fedrau
Set 100BT1 and 1000BT1 linkmode advertisement bits to adv_l_mask to enable detection. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> Link: https://lore.kernel.org/r/20240218075753.18067-4-dima.fedrau@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-21net: phy: mxl-gpy: fill in possible_interfaces for GPY21x chipsetRaju Lakkaraju
Fill in the possible_interfaces member. GPY21x phys support the SGMII and 2500base-X interfaces Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microchip.com> Link: https://lore.kernel.org/r/20240216054435.22380-1-Raju.Lakkaraju@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-18net: phy: aquantia: add AQR813 PHY IDChristian Marangi
Aquantia AQR813 is the Octal Port variant of the AQR113. Add PHY ID for it to provide support for it. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-17net: phy: c45: add support for MDIO_AN_EEE_ADV2Heiner Kallweit
Add support for handling the EEE advertisement 2 register. For now only 2500baseT and 5000baseT modes are supported. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-17net: phy: c45: add support for EEE link partner ability 2 to ↵Heiner Kallweit
genphy_c45_read_eee_lpa Add support for reading EEE link partner ability 2 register. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-17net: phy: c45: add and use genphy_c45_read_eee_cap2Heiner Kallweit
Add and use genphy_c45_read_eee_cap2(), complementing genphy_c45_read_eee_cap1(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-17net: phy: add PHY_EEE_CAP2_FEATURESHeiner Kallweit
As a prerequisite for adding EEE CAP2 register support, complement PHY_EEE_CAP1_FEATURES with PHY_EEE_CAP2_FEATURES. For now only 2500baseT and 5000baseT modes are supported. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-16net: phy: aquantia: add AQR113 PHY IDChristian Marangi
Add Aquantia AQR113 PHY ID. Aquantia AQR113 is just a chip size variant of the already supported AQR133C where the only difference is the PHY ID and the hw chip size. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-15Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR. No conflicts. Adjacent changes: net/core/dev.c 9f30831390ed ("net: add rcu safety to rtnl_prop_list_size()") 723de3ebef03 ("net: free altname using an RCU callback") net/unix/garbage.c 11498715f266 ("af_unix: Remove io_uring code for GC.") 25236c91b5ab ("af_unix: Fix task hung while purging oob_skb in GC.") drivers/net/ethernet/renesas/ravb_main.c ed4adc07207d ("net: ravb: Count packets instead of descriptors in GbEth RX path" ) c2da9408579d ("ravb: Add Rx checksum offload support for GbEth") net/mptcp/protocol.c bdd70eb68913 ("mptcp: drop the push_pending field") 28e5c1380506 ("mptcp: annotate lockless accesses around read-mostly fields") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-15net: fill in MODULE_DESCRIPTION()s for mdio_devresBreno Leitao
W=1 builds now warn if module is built without a MODULE_DESCRIPTION(). Add descriptions to the PHY MDIO helpers. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Breno Leitao <leitao@debian.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240214152741.670178-7-leitao@debian.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-15net: mdio_bus: make mdio_bus_type constRicardo B. Marliere
Since commit d492cc2573a0 ("driver core: device.h: make struct bus_type a const *"), the driver core can properly handle constant struct bus_type, move the mdio_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Suggested-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Ricardo B. Marliere <ricardo@marliere.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20240213-bus_cleanup-mdio-v1-1-f9e799da7fda@marliere.net Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-02-15net: phy: aquantia: add AQR111 and AQR111B0 PHY IDChristian Marangi
Add Aquantia AQR111 and AQR111B0 PHY ID. These PHY advertise 10G speed but actually supports up to 5G speed, hence some manual fixup is needed. The Aquantia AQR111B0 PHY is just a variant of the AQR111 with smaller chip size. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240213133558.1836-1-ansuelsmth@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-02-15net: phy: qca807x: move interface mode check to .config_init_onceRobert Marko
Currently, we are checking whether the PHY package mode matches the individual PHY interface modes at PHY package probe time, but at that time we only know the PHY package mode and not the individual PHY interface modes as of_get_phy_mode() that populates it will only get called once the netdev to which PHY-s are attached to is being probed and thus this check will always fail and return -EINVAL. So, lets move this check to .config_init_once as at that point individual PHY interface modes should be populated. Fixes: d1cb613efbd3 ("net: phy: qcom: add support for QCA807x PHY Family") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240212115043.1725918-1-robimarko@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-02-14net: phy: dp83826: support TX data voltage tuningCatalin Popescu
DP83826 offers the possibility to tune the voltage of logical levels of the MLT-3 encoded TX data. This is useful when there is a voltage drop in between the PHY and the connector and we want to increase the voltage levels to compensate for that drop. Prior to PHY configuration, the driver SW resets the PHY which has the same effect as the HW reset pin according to the datasheet. Hence, there's no need to force update the VOD_CFG registers to make sure they hold their reset values. VOD_CFG registers need to be updated only if the DT has been configured with values other than the reset ones. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Catalin Popescu <catalin.popescu@leica-geosystems.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-13net: phy: aquantia: clear PMD Global Transmit Disable bit during initRobert Marko
PMD Global Transmit Disable bit should be cleared for normal operation. This should be HW default, however I found that on Asus RT-AX89X that uses AQR113C PHY and firmware 5.4 this bit is set by default. With this bit set the AQR cannot achieve a link with its link-partner and it took me multiple hours of digging through the vendor GPL source to find this out, so lets always clear this bit during .config_init() to avoid a situation like this in the future. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240211181732.646311-1-robimarko@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-02-10net: phy: qca807x: add support for configurable LEDChristian Marangi
QCA8072/5 have up to 2 LEDs attached for PHY. LEDs can be configured to be ON/hw blink or be set to HW control. Hw blink mode is set to blink at 4Hz or 250ms. PHY can support both copper (TP) or fiber (FIBRE) kind and supports different HW control modes based on the port type. HW control modes supported for netdev trigger for copper ports are: - LINK_10 - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX HW control modes supported for netdev trigger for fiber ports are: - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX LED support conflicts with GPIO controller feature and must be disabled if gpio-controller is used for the PHY. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: qcom: generalize some qca808x LED functionsChristian Marangi
Generalize some qca808x LED functions in preparation for qca807x LED support. The LED implementation of qca808x and qca807x is the same but qca807x supports also Fiber port and have different hw control bits for Fiber port. To limit code duplication introduce micro functions that takes reg instead of LED index to tweak all the supported LED modes. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: qcom: move common qca808x LED define to shared headerChristian Marangi
The LED implementation of qca808x and qca807x is the same but qca807x supports also Fiber port and have different hw control bits for Fiber port. In preparation for qca807x introduction, move all the common define to shared header. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: qcom: add support for QCA807x PHY FamilyRobert Marko
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber. PHY package can be configured in 3 mode following this table: First Serdes mode Second Serdes mode Option 1 PSGMII for copper Disabled ports 0-4 Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX ports 0-4 Option 3 QSGMII for copper SGMII for ports 0-3 copper port 4 Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s. But some vendors used these to driver generic LED-s controlled by userspace, so lets enable registering each PHY as GPIO controller and add driver for it. These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. Co-developed-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: provide whether link has changed in c37_read_statusChristian Marangi
Some PHY driver might require additional regs call after genphy_c37_read_status() is called. Expand genphy_c37_read_status to provide a bool wheather the link has changed or not to permit PHY driver to skip additional regs call if nothing has changed. Every user of genphy_c37_read_status() is updated with the new additional bool. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: qcom: move more function to shared libraryChristian Marangi
Move more function to shared library in preparation for introduction of new PHY Family qca807x that will make use of both functions from at803x and qca808x as it's a transition PHY with some implementation of at803x and some from the new qca808x. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: add devm/of_phy_package_join helperChristian Marangi
Add devm/of_phy_package_join helper to join PHYs in a PHY package. These are variant of the manual phy_package_join with the difference that these will use DT nodes to derive the base_addr instead of manually passing an hardcoded value. An additional value is added in phy_package_shared, "np" to reference the PHY package node pointer in specific PHY driver probe_once and config_init_once functions to make use of additional specific properties defined in the PHY package node in DT. The np value is filled only with of_phy_package_join if a valid PHY package node is found. A valid PHY package node must have the node name set to "ethernet-phy-package". Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-10net: phy: add support for scanning PHY in PHY packages nodesChristian Marangi
Add support for scanning PHY in PHY package nodes. PHY packages nodes are just container for actual PHY on the MDIO bus. Their PHY address defined in the PHY package node are absolute and reflect the address on the MDIO bus. mdio_bus.c and of_mdio.c is updated to now support and parse also PHY package subnode by checking if the node name match "ethernet-phy-package". As PHY package reg is mandatory and each PHY in the PHY package must have a reg, every invalid PHY Package node is ignored and will be skipped by the autoscan fallback. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-09net: phy: realtek: use generic MDIO helpers to simplify the codeHeiner Kallweit
Use generic MDIO helpers to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/422ae70f-7305-45fd-ab3e-0dd604b9fd6c@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-07net: phy: realtek: add 5Gbps support to rtl822x_config_aneg()Heiner Kallweit
RTL8126 as an evolution of RTL8125 supports 5Gbps. rtl822x_config_aneg() is used by the PHY driver for the integrated PHY, therefore add 5Gbps support to it. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://lore.kernel.org/r/5644ab50-e3e9-477c-96db-05cd5bdc2563@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-07net: phy: realtek: use generic MDIO constantsMarek Behún
Drop the ad-hoc MDIO constants used in the driver and use generic constants instead. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/732a70d6-4191-4aae-8862-3716b062aa9e@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-07net: phy: c45 scanning: Don't consider -ENODEV fatalAndrew Lunn
When scanning the MDIO bus for C22 devices, the driver returning -ENODEV is not considered fatal, it just indicates the MDIO bus master knows there is no device at that address, maybe because of hardware limitation. Make the C45 scan code act on -ENODEV the same way, to make C22 and C45 more uniform. It is expected all reads for a given address will return -ENODEV, so within get_phy_c45_ids() only the first place a read occurs has been changed. Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-06net: phy: add helper phy_advertise_eee_allHeiner Kallweit
Per default phylib preserves the EEE advertising at the time of phy probing. The EEE advertising can be changed from user space, in addition this helper allows to set the EEE advertising to all supported modes from drivers in kernel space. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20bfc471-aeeb-4ae4-ba09-7d6d4be6b86a@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-06net: phy: constify phydev->drvRussell King (Oracle)
Device driver structures are shared between all devices that they match, and thus nothing should never write to the device driver structure through the phydev->drv pointer. Let's make this pointer const to catch code that attempts to do so. Suggested-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/E1rVxXt-002YqY-9G@rmk-PC.armlinux.org.uk Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-02-04net: micrel: Fix the frequency adjustmentsHoratiu Vultur
By default lan8841's 1588 clock frequency is 125MHz. But when adjusting the frequency, it is using the 1PPM format of the lan8814. Which is the wrong format as lan8814 has a 1588 clock frequency of 250MHz. So then for each 1PPM adjustment would adjust less than expected. Therefore fix this by using the correct 1PPM format for lan8841. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-03net: phy: qcom: qca808x: default to LED active High if not setChristian Marangi
qca808x PHY provide support for the led_polarity_set OP to configure and apply the active-low property but on PHY reset, the Active High bit is not set resulting in the LED driven as active-low. To fix this, check if active-low is not set in DT and enable Active High polarity by default to restore correct funcionality of the LED. Fixes: 7196062b64ee ("net: phy: at803x: add LED support for qca808x") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-03net: phy: qcom: qca808x: fix logic error in LED brightness setChristian Marangi
In switching to using phy_modify_mmd and a more short version of the LED ON/OFF condition in later revision, it was made a logic error where value ? QCA808X_LED_FORCE_ON : QCA808X_LED_FORCE_OFF is always true as value is always OR with QCA808X_LED_FORCE_EN due to missing () resulting in the testing condition being QCA808X_LED_FORCE_EN | value. Add the () to apply the correct condition and restore correct functionality of the brightness ON/OFF. Fixes: 7196062b64ee ("net: phy: at803x: add LED support for qca808x") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-02net: phy: realtek: add support for RTL8126A-integrated 5Gbps PHYHeiner Kallweit
A user reported that first consumer mainboards show up with a RTL8126A 5Gbps MAC/PHY. This adds support for the integrated PHY, which is also available stand-alone. From a PHY driver perspective it's treated the same as the 2.5Gbps PHY's, we just have to support the new PHY ID. Reported-by: Joe Salmeri <jmscdba@gmail.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Joe Salmeri <jmscdba@gmail.com> Link: https://lore.kernel.org/r/0c8e67ea-6505-43d1-bd51-94e7ecd6e222@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-02-02net: phy: dp83867: Add support for active-low LEDsAlexander Stein
Add the led_polarity_set callback for setting LED polarity. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-02-01Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR. No conflicts or adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: qcom: detach qca808x PHY driver from at803xChristian Marangi
Almost all the QCA8081 PHY driver OPs are specific and only some of them use the generic at803x. To make the at803x code slimmer, move all the specific qca808x regs and functions to a dedicated PHY driver. Probe function and priv struct is reworked to allocate and use only the qca808x specific data. Unused data from at803x PHY driver are dropped from at803x priv struct. Also a new Kconfig is introduced QCA808X_PHY, to compile the newly introduced PHY driver for QCA8081 PHY. As the Kconfig name starts with Qualcomm the same order is kept. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129141600.2592-6-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: qcom: move additional functions to shared libraryChristian Marangi
Move additional functions to shared library in preparation for qca808x PHY Family to be detached from at803x driver. Only the shared defines are moved to the shared qcom.h header. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129141600.2592-5-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: qcom: deatch qca83xx PHY driver from at803xChristian Marangi
Deatch qca83xx PHY driver from at803x. The QCA83xx PHYs implement specific function and doesn't use generic at803x so it can be detached from the driver and moved to a dedicated one. Probe function and priv struct is reimplemented to allocate and use only the qca83xx specific data. Unused data from at803x PHY driver are dropped from at803x priv struct. This is to make slimmer PHY drivers instead of including lots of bloat that would never be used in specific SoC. A new Kconfig flag QCA83XX_PHY is introduced to compile the new introduced PHY driver. As the Kconfig name starts with Qualcomm the same order is kept. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129141600.2592-4-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: qcom: create and move functions to shared libraryChristian Marangi
Create and move functions to shared library in preparation for qca83xx PHY Family to be detached from at803x driver. Only the shared defines are moved to the shared qcom.h header. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: move at803x PHY driver to dedicated directoryChristian Marangi
In preparation for addition of other Qcom PHY and to tidy things up, move the at803x PHY driver to dedicated directory. The same order in the Kconfig selection is saved. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129141600.2592-2-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: adin1100: Add interrupt support for link changeAndre Werner
An interrupt handler was added to the driver as well as functions to enable interrupts at the phy. There are several interrupts maskable at the phy, but only link change interrupts are handled by the driver yet. Signed-off-by: Andre Werner <andre.werner@systec-electronic.com> Link: https://lore.kernel.org/r/20240129135734.18975-3-andre.werner@systec-electronic.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: phy_device: Prevent nullptr exceptions on ISRAndre Werner
If phydev->irq is set unconditionally, check for valid interrupt handler or fall back to polling mode to prevent nullptr exceptions in interrupt service routine. Signed-off-by: Andre Werner <andre.werner@systec-electronic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240129135734.18975-2-andre.werner@systec-electronic.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-31net: phy: c45: change genphy_c45_ethtool_[get|set]_eee to use EEE linkmode ↵Heiner Kallweit
bitmaps Change genphy_c45_ethtool_[get|set]_eee to use EEE linkmode bitmaps. This is a prerequisite for adding support for EEE modes beyond bit 31. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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